Add cut 1 of a cellram module

[fpgaboy.git] / LCDC.v

diff --git a/LCDC.v b/LCDC.v
index 7b402e4fdf7fab3d3f56a0e8e6526085320e38e8..a198c45d03ad806e4987cf3c3b7455ee9e704745 100644 (file)
--- a/LCDC.v
+++ b/LCDC.v
@@ -27,7 +27,7 @@ module LCDC(
        /***** Internal clock that is stable and does not depend on CPU in single/double clock mode *****/
        reg clk4 = 0;
        always @(posedge clk)
-               clk4 = ~clk4;
+               clk4 <= ~clk4;
        
        /***** LCD control registers *****/
        reg [7:0] rLCDC = 8'h00;
@@ -154,14 +154,13 @@ module LCDC(
        wire [9:0] bgmapaddr_in = vraminuse ? bgmapaddr : addr[9:0];
        wire [11:0] tileaddr_in = vraminuse ? tileaddr : addr[12:1];
        
-       always @(negedge clk)
+       always @(posedge clk)
+       begin
                if ((vraminuse && ((posx == 2) || (vxpos[2:0] == 3'b111))) || decode_bgmap1) begin
                        tileno <= bgmap1[bgmapaddr_in];
                        if (wr && decode_bgmap1 && ~vraminuse)
                                bgmap1[bgmapaddr_in] <= data;
                end
-       
-       always @(negedge clk)
                if ((vraminuse && ((posx == 3) || (vxpos[2:0] == 3'b000))) || decode_tiledata) begin
                        tilehigh <= tiledatahigh[tileaddr_in];
                        tilelow <= tiledatalow[tileaddr_in];
@@ -170,6 +169,7 @@ module LCDC(
                        if (wr && ~addr[0] && decode_tiledata && ~vraminuse)
                                tiledatalow[tileaddr_in] <= data;
                end
+       end
   
        /***** Bus interface *****/
        assign data = rd ?
@@ -190,7 +190,7 @@ module LCDC(
                         8'bzzzzzzzz) :
                8'bzzzzzzzz;
   
-       always @(negedge clk)
+       always @(posedge clk)
        begin
                if (wr)
                        case (addr)