Soundcore compiles

[fpgaboy.git] / Soundcore.v

diff --git a/Soundcore.v b/Soundcore.v
new file mode 100644 (file)
index 0000000..172ed4f
--- /dev/null
+++ b/Soundcore.v
@@ -0,0 +1,71 @@
+`define ADDR_NR50 16'hFF24
+`define ADDR_NR51 16'hFF25
+`define ADDR_NR52 16'hFF26
+
+module Soundcore(
+       input core_clk,
+       input wr,
+       input rd,
+       input [15:0] addr,
+       inout [7:0] data,
+       output reg snd_data_l,
+       output reg snd_data_r
+       );
+
+       reg [7:0] nr50,nr51,nr52;
+       reg [3:0] pwmcnt;
+       reg [4:0] cntclk;
+       reg [13:0] lenclk;
+       wire [3:0] sndout1,sndout2,sndout3,sndout4;
+       wire [3:0] right_snd = nr51[0] ? sndout1 : 4'b0;
+       wire [3:0] left_snd = nr51[4] ? sndout1 : 4'b0;
+
+       assign sndout3 = 0;
+       assign sndout4 = 0;
+
+       assign data = rd ?
+                        addr == `ADDR_NR50 ? nr50 :
+                        addr == `ADDR_NR51 ? nr51 :
+                        addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
+                     : 8'bzzzzzzzz;
+
+       always @ (negedge core_clk) begin
+               if(wr) begin
+                       case(addr)
+                       `ADDR_NR50: nr50 <= data;
+                       `ADDR_NR51: nr51 <= data;
+                       `ADDR_NR52: nr52 <= {data[7],3'b1,data[3:0]};
+                       endcase
+               end
+               cntclk <= cntclk + 1;
+               lenclk <= lenclk + 1;
+               pwmcnt <= pwmcnt + 1; 
+               snd_data_l <= (pwmcnt <= left_snd) ? 1 : 0;
+               snd_data_r <= (pwmcnt <= right_snd) ? 1 : 0;
+       end
+
+       Sound1(
+               .core_clk(core_clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .cntclk(cntclk[4]),
+               .lenclk(lenclk[13]),
+               .en(nr52[7] & nr52[0]),
+               .snd_data(sndout1)
+       );
+       
+       Sound2(
+               .core_clk(core_clk),
+               .wr(wr),
+               .rd(rd),
+               .addr(addr),
+               .data(data),
+               .cntclk(cntclk[4]),
+               .lenclk(lenclk[13]),
+               .en(nr52[7] & nr52[0]),
+               .snd_data(sndout2)
+       );
+
+endmodule