Dual boot ROM support, and the first proof that cellular ram works!

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index b06910a6c3052f3c8648424e6926aac0a8953ce5..e1aa3087b0a94f4cb7e422c3160b7849bf334c5a 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -177,17 +177,21 @@ module GBZ80Core(
        
        reg bootstrap_enb;
        
        
        reg bootstrap_enb;
        

-       wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF));  /* 0 or 1 depending on which bus */
+       wire bus = ((busaddress[15:8] == 8'h00) && bootstrap_enb) || ((busaddress[15:7] == 9'b111111111) && (busaddress != 16'hFFFF))   /* 0 or 1 depending on which bus */
+               `ifdef isim
+                       || (busaddress === 16'hxxxx) /* To avoid simulator glomulation. */
+               `endif
+                       ;

                
        assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
        assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
        assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
        assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
        assign busdata = (bus == 0) ? bus0data : bus1data;
                
        assign bus0address = (bus == 0) ? busaddress : 16'bzzzzzzzzzzzzzzz;
        assign bus1address = (bus == 1) ? busaddress : 16'bzzzzzzzzzzzzzzz;
        assign bus0data = ((bus == 0) && buswr) ? buswdata : 8'bzzzzzzzz;
        assign bus1data = ((bus == 1) && buswr) ? buswdata : 8'bzzzzzzzz;
        assign busdata = (bus == 0) ? bus0data : bus1data;

-       assign bus0rd = (bus == 0) ? busrd : 1'bz;
-       assign bus1rd = (bus == 1) ? busrd : 1'bz;
-       assign bus0wr = (bus == 0) ? buswr : 1'bz;
-       assign bus1wr = (bus == 1) ? buswr : 1'bz;
+       assign bus0rd = (bus == 0) ? busrd : 1'b0;
+       assign bus1rd = (bus == 1) ? busrd : 1'b0;
+       assign bus0wr = (bus == 0) ? buswr : 1'b0;
+       assign bus1wr = (bus == 1) ? buswr : 1'b0;

 
        reg ie, iedelay;
 
 
        reg ie, iedelay;
 


@@ -296,6 +300,8 @@ module GBZ80Core(
                        end
                end
                `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
                        end
                end
                `STATE_DECODE: begin    /* Make sure this only happens for one clock. */

+                       buswr <= 0;
+                       busrd <= 0;

                end
                endcase
        
                end
                endcase
        


@@ -314,11 +320,11 @@ module GBZ80Core(
                                        opcode <= `INSN_VOP_INTR;
                                else
                                        opcode <= {1'b0,busdata};
                                        opcode <= `INSN_VOP_INTR;
                                else
                                        opcode <= {1'b0,busdata};

-                               rdata <= busdata;

                                newcycle <= 0;
                                newcycle <= 0;

+                               rdata <= busdata;

                                cycle <= 0;
                        end else begin
                                cycle <= 0;
                        end else begin

-                               if (rd) rdata <= busdata;
+                               if (rd) rdata <= busdata;       /* Still valid because peripherals are now expected to keep it held valid. */

                                cycle <= cycle + 1;
                        end
                        if (iedelay) begin
                                cycle <= cycle + 1;
                        end
                        if (iedelay) begin


@@ -327,13 +333,13 @@ module GBZ80Core(
                        end
                        wr <= 0;
                        rd <= 0;
                        end
                        wr <= 0;
                        rd <= 0;

-                       buswr <= 0;
-                       busrd <= 0;

                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
                        address <= 16'bxxxxxxxxxxxxxxxx;        // Make it obvious if something of type has happened.
                        wdata <= 8'bxxxxxxxx;
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin

+                       if (opcode[7:0] === 8'bxxxxxxxx)
+                               $stop;

                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"