+module ROM(
+ input [15:0] address,
+ inout [7:0] data,
+ input wr, rd);
+
+ reg [7:0] rom [2047:0];
+ initial $readmemh("rom.hex", rom);
+
+ wire decode = address[15:13] == 0;
+ reg [7:0] odata;
+ wire idata = data;
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+ always @(posedge rd)
+ if (decode)
+ odata <= rom[address];
+endmodule
+
+module InternalRAM(
+ input [15:0] address,
+ inout [7:0] data,
+ input clk,
+ input wr, rd);
+
+ reg [7:0] ram [8191:0];
+
+ wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+ reg [7:0] odata;
+ wire idata = data;
+ assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+
+ reg [13:0] diq;
+ initial
+ for (diq = 0; diq < 8191; diq = diq + 1)
+ ram[diq] = 8'h43;
+
+ always @(negedge clk)
+ begin
+ if (decode && rd)
+ odata <= ram[address[12:0]];
+ if (decode && wr)
+ ram[address[12:0]] <= data;
+ end
+endmodule
+