Fix some really dumb no-synthesize issues LIKE NOT TYPING THE MODULE NAME CORRECTLY...

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index ebc9be4eb6d1ed10d39723031aeb83286a983d42..b1d4c3d90241b3aaab8ac4f103e1dbf292c177b9 100644 (file)
--- a/System.v
+++ b/System.v
@@ -28,13 +28,16 @@ module BootstrapROM(
        input wr, rd);
 
        reg rdlatch = 0;
+       reg [7:0] addrlatch = 0;
        reg [7:0] brom [255:0];
        initial $readmemh("bootstrap.hex", brom);
 
        wire decode = address[15:8] == 0;
-       wire [7:0] odata = brom[address[7:0]];
-       always @(posedge clk)
+       wire [7:0] odata = brom[addrlatch];
+       always @(posedge clk) begin
                rdlatch <= rd && decode;
+               addrlatch <= address[7:0];
+       end
        assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule
 
@@ -259,11 +262,11 @@ module CoreTop(
                .data(data[0]),
                .clk(clk),
                .wr(wr[0]),
-               .rd(rd[0])
+               .rd(rd[0]),
                .cr_nADV(cr_nADV),
                .cr_nCE(cr_nCE),
                .cr_nOE(cr_nOE),
-               .cr_nWR(cr_nWE),
+               .cr_nWE(cr_nWE),
                .cr_CRE(cr_CRE),
                .cr_nLB(cr_nLB),
                .cr_nUB(cr_nUB),