Diag rom now runs from bootloader!

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index ebc9be4eb6d1ed10d39723031aeb83286a983d42..55dda1c1d1140fd1996169715efa066c50c04383 100644 (file)
--- a/System.v
+++ b/System.v
@@ -28,13 +28,22 @@ module BootstrapROM(
        input wr, rd);
 
        reg rdlatch = 0;
        input wr, rd);
 
        reg rdlatch = 0;

-       reg [7:0] brom [255:0];
-       initial $readmemh("bootstrap.hex", brom);
+       reg [7:0] addrlatch = 0;
+       reg romno = 0, romnotmp = 0;
+       reg [7:0] brom0 [255:0];
+       reg [7:0] brom1 [255:0];
+       
+       initial $readmemh("fpgaboot.hex", brom0);
+       initial $readmemh("gbboot.hex", brom1);

 
        wire decode = address[15:8] == 0;
 
        wire decode = address[15:8] == 0;

-       wire [7:0] odata = brom[address[7:0]];
-       always @(posedge clk)
+       wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
+       always @(posedge clk) begin

                rdlatch <= rd && decode;
                rdlatch <= rd && decode;

+               addrlatch <= address[7:0];
+               if (wr && decode) romnotmp <= data[0];
+               if (rd && address == 16'h0000) romno <= romnotmp;       /* Latch when the program restarts. */
+       end

        assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule
 
        assign data = rdlatch ? odata : 8'bzzzzzzzz;
 endmodule
 


@@ -83,6 +92,8 @@ module CellularRAM(
        
        reg [7:0] progaddrh, progaddrm, progaddrl;
        
        
        reg [7:0] progaddrh, progaddrm, progaddrl;
        

+       reg [22:0] progaddr;
+       

        assign cr_nADV = 0;     /* Addresses are always valid! :D */
        assign cr_nCE = 0;      /* The chip is enabled */
        assign cr_nLB = 0;      /* Lower byte is enabled */
        assign cr_nADV = 0;     /* Addresses are always valid! :D */
        assign cr_nCE = 0;      /* The chip is enabled */
        assign cr_nLB = 0;      /* Lower byte is enabled */


@@ -96,9 +107,9 @@ module CellularRAM(
        assign cr_nWE = decode ? ~wrlatch : 1;
        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
        assign cr_nWE = decode ? ~wrlatch : 1;
        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};

-       assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom */ {9'b0,addrlatch[13:0]} :
-                       (addrlatch[15:13] == 3'b101) ? {1'b1, 9'b0, addrlatch[12:0]} :
-                       (addrlatch == ADDR_PROGDATA) ? {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} :
+       assign cr_A = (address[15:14] == 2'b00) ? /* extrom */ {9'b0,address[13:0]} :
+                       (address[15:13] == 3'b101) ? {1'b1, 9'b0, address[12:0]} :
+                       (address == ADDR_PROGDATA) ? progaddr :

                        23'b0;
        
        reg [7:0] regbuf;
                        23'b0;
        
        reg [7:0] regbuf;


@@ -108,6 +119,10 @@ module CellularRAM(
                ADDR_PROGADDRH: if (wr) progaddrh <= data;
                ADDR_PROGADDRM: if (wr) progaddrm <= data;
                ADDR_PROGADDRL: if (wr) progaddrl <= data;
                ADDR_PROGADDRH: if (wr) progaddrh <= data;
                ADDR_PROGADDRM: if (wr) progaddrm <= data;
                ADDR_PROGADDRL: if (wr) progaddrl <= data;

+               ADDR_PROGDATA:  if (rd || wr) begin
+                                       progaddr <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]};
+                                       {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} <= {progaddrh[6:0], progaddrm[7:0], progaddrl[7:0]} + 23'b1;
+                               end

                endcase
                rdlatch <= rd;
                wrlatch <= wr;
                endcase
                rdlatch <= rd;
                wrlatch <= wr;


@@ -187,6 +202,7 @@ module CoreTop(
        input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        input [3:0] buttons,
        output wire [7:0] leds,
        output serio,

+       input serin,

        output wire [3:0] digits,
        output wire [7:0] seven,
        output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,
        output wire [3:0] digits,
        output wire [7:0] seven,
        output wire cr_nADV, cr_nCE, cr_nOE, cr_nWE, cr_CRE, cr_nLB, cr_nUB, cr_CLK,


@@ -206,6 +222,7 @@ module CoreTop(
        
        wire [7:0] leds;
        wire serio;
        
        wire [7:0] leds;
        wire serio;

+       wire serin = 1;

        wire [3:0] digits;
        wire [7:0] seven;
        wire [7:0] switches = 8'b0;
        wire [3:0] digits;
        wire [7:0] seven;
        wire [7:0] switches = 8'b0;


@@ -259,11 +276,11 @@ module CoreTop(
                .data(data[0]),
                .clk(clk),
                .wr(wr[0]),
                .data(data[0]),
                .clk(clk),
                .wr(wr[0]),

-               .rd(rd[0])
+               .rd(rd[0]),

                .cr_nADV(cr_nADV),
                .cr_nCE(cr_nCE),
                .cr_nOE(cr_nOE),
                .cr_nADV(cr_nADV),
                .cr_nCE(cr_nCE),
                .cr_nOE(cr_nOE),

-               .cr_nWR(cr_nWE),
+               .cr_nWE(cr_nWE),

                .cr_CRE(cr_CRE),
                .cr_nLB(cr_nLB),
                .cr_nUB(cr_nUB),
                .cr_CRE(cr_CRE),
                .cr_nLB(cr_nLB),
                .cr_nUB(cr_nUB),


@@ -333,7 +350,8 @@ module CoreTop(
                .data(data[0]),
                .wr(wr[0]),
                .rd(rd[0]),
                .data(data[0]),
                .wr(wr[0]),
                .rd(rd[0]),

-               .serial(serio)
+               .serial(serio),
+               .serialrx(serin)

                );
 
        InternalRAM ram(
                );
 
        InternalRAM ram(