Set up the bus a little before the clock.

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index a036c64e5ad7858422f27515730da6d13c15c9d0..1f0ae7d0d31c57fbc648a6aab693e9fbd77fc367 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -1,5 +1,5 @@
 `define IN_CLK 8388608
-`define OUT_CLK 9600
+`define OUT_CLK 57600
 `define CLK_DIV `IN_CLK / `OUT_CLK
 `define MMAP_ADDR 16'hFF50
 
@@ -9,7 +9,7 @@ module UART(
        input rd,
        input [15:0] addr,
        inout [7:0] data,
-       output reg serial);
+       output reg serial = 1);
        
        wire decode = (addr == `MMAP_ADDR);
        
@@ -19,17 +19,16 @@ module UART(
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
        reg have_data = 0;
-       reg data_end = 0;
        reg [3:0] diqing = 4'b0000;
        
-       wire new = (wr) && (!have_data) && decode;
+       wire newdata = (wr) && (!have_data) && decode;
        
        assign odata = have_data ? 8'b1 : 8'b0;
 
        always @ (negedge clk)
        begin
                /* deal with diqing */
-               if(new) begin
+               if(newdata) begin
                        data_stor <= data;
                        have_data <= 1;
                        diqing <= 4'b0000;
@@ -53,7 +52,7 @@ module UART(
                end
 
                /* deal with clkdiv */
-               if((new && !have_data) || clkdiv == `CLK_DIV)
+               if((newdata && !have_data) || clkdiv == `CLK_DIV)
                        clkdiv <= 0;
                else
                        clkdiv <= clkdiv + 1;