Tweak the sign on a bit

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 53e6257f601762ceb5ecd2e27de03eed8c0c029b..996ec1092c1973a86f85b9ba24e5099ac301f31c 100644 (file)
--- a/System.v
+++ b/System.v
@@ -21,19 +21,22 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
+       // synthesis attribute ram_style of reg is block
        reg [7:0] ram [8191:0];
        
-       wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+       wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
-               if (decode && rd)
+               if (decode)
+               begin
+                       if (wr)
+                               ram[address[12:0]] <= data;
                        odata <= ram[address[12:0]];
-               else if (decode && wr)
-                       ram[address[12:0]] <= data;
+               end
        end
 endmodule
 
@@ -61,6 +64,7 @@ endmodule
 module CoreTop(
        input xtal,
        input [7:0] switches,
+       input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
@@ -93,7 +97,8 @@ module CoreTop(
     .addr(addr), 
     .clk(clk), 
     .digit(digits), 
-    .out(seven)
+    .out(seven),
+        .freeze(buttons[0])
     );
         
        Switches sw(
@@ -114,6 +119,13 @@ module CoreTop(
     .data(data), 
     .serial(serio)
     );
+
+  InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));
 endmodule
 
 module TestBench();
@@ -140,21 +152,21 @@ module TestBench();
                .wr(wr),
                .rd(rd));
        
-//     InternalRAM ram(
-//             .address(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd));
+       InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));
 
-//     wire serio;
-//     UART uart(
-//             .addr(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd),
-//             .serial(serio));
+       wire serio;
+       UART uart(
+               .addr(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .serial(serio));
        
 //     Switches sw(
 //             .clk(clk),