Tweak the sign on a bit

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1bc8f78fb6c06abc2205cef6f1dc92cf1d888358..0f0496eed4200d7e2f98b8ac9a8ffd3e3952608a 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -39,6 +39,7 @@
 `define INSN_CALL                              8'b11001101
 `define INSN_JP_imm                    8'b11000011
 `define INSN_JPCC_imm          8'b110xx010
+`define INSN_ALU_A             8'b00xxx111
 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01
@@ -69,6 +70,14 @@
 `define INSN_alu_XOR           3'b101
 `define INSN_alu_OR            3'b110
 `define INSN_alu_CP            3'b111          // Oh lawd, is dat some CP?
+`define INSN_alu_RLCA          3'b000
+`define INSN_alu_RRCA          3'b001
+`define INSN_alu_RLA           3'b010
+`define INSN_alu_RRA           3'b011
+`define INSN_alu_DAA           3'b100
+`define INSN_alu_CPL           3'b101
+`define INSN_alu_SCF           3'b110
+`define INSN_alu_CCF           3'b111
 
 module GBZ80Core(
        input clk,
@@ -357,6 +366,10 @@ module GBZ80Core(
                                        endcase
                                end
                        end
+                       `INSN_ALU_A: begin
+                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC;
+                       end
                        `INSN_NOP: begin
                                `EXEC_NEWCYCLE;
                                `EXEC_INC_PC;
@@ -443,13 +456,14 @@ module GBZ80Core(
                                                rd <= 1;
                                        end
                                2:      begin
+                                               `EXEC_INC_PC;
                                                if (!opcode[0]) begin   // i.e., JP cc,nn
                                                        /* We need to check the condition code to bail out. */
                                                        case (opcode[4:3])
                                                        `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_Z:             if (!registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
                                                        `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
-                                                       `INSN_cc_C:             if (!registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
                                                        endcase
                                                end
                                        end
@@ -622,6 +636,28 @@ module GBZ80Core(
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
+                                       `INSN_alu_SUB: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] - tmp;
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b1,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
+                                       `INSN_alu_SBC: begin
+                                               registers[`REG_A] <=
+                                                       registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b1,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
                                        `INSN_alu_AND: begin
                                                registers[`REG_A] <=
                                                        registers[`REG_A] & tmp;
@@ -649,11 +685,50 @@ module GBZ80Core(
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
+                                       `INSN_alu_CP: begin
+                                               registers[`REG_F] <=
+                                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+                                                         /* N */ 1'b1,
+                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+                                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+                                                         registers[`REG_F][3:0]
+                                                       };
+                                       end
                                        default:
                                                $stop;
                                        endcase
                                end
                        end
+                       `INSN_ALU_A: begin
+                               case(opcode[5:3])
+                               `INSN_alu_RLCA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_RRCA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_RLA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_RRA: begin
+                                       registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_CPL: begin
+                                       registers[`REG_A] <= ~registers[`REG_A];
+                                       registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
+                               end
+                               `INSN_alu_SCF: begin
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+                               end
+                               `INSN_alu_CCF: begin
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
+                               end
+                               endcase
+                       end
                        `INSN_NOP: begin /* NOP! */ end
                        `INSN_RST: begin
                                case (cycle)