`define INSN_NOP 8'b00000000
`define INSN_RST 8'b11xxx111
`define INSN_RET 8'b110x1001 // 1 = RETI, 0 = RET
+`define INSN_RETCC 8'b110xx000
`define INSN_CALL 8'b11001101
+`define INSN_CALLCC 8'b110xx100 // Not that call/cc.
`define INSN_JP_imm 8'b11000011
`define INSN_JPCC_imm 8'b110xx010
+`define INSN_ALU_A 8'b00xxx111
+`define INSN_JP_HL 8'b11101001
+`define INSN_JR_imm 8'b00011000
+`define INSN_JRCC_imm 8'b001xx000
+`define INSN_INCDEC16 8'b00xxx011
`define INSN_cc_NZ 2'b00
`define INSN_cc_Z 2'b01
`define INSN_alu_XOR 3'b101
`define INSN_alu_OR 3'b110
`define INSN_alu_CP 3'b111 // Oh lawd, is dat some CP?
+`define INSN_alu_RLCA 3'b000
+`define INSN_alu_RRCA 3'b001
+`define INSN_alu_RLA 3'b010
+`define INSN_alu_RRA 3'b011
+`define INSN_alu_DAA 3'b100
+`define INSN_alu_CPL 3'b101
+`define INSN_alu_SCF 3'b110
+`define INSN_alu_CCF 3'b111
module GBZ80Core(
input clk,
- output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
+ output reg [15:0] busaddress = 0, /* BUS_* is latched on STATE_FETCH. */
inout [7:0] busdata,
- output reg buswr, output reg busrd);
+ output reg buswr = 0, output reg busrd = 0);
reg [1:0] state = 0; /* State within this bus cycle (see STATE_*). */
reg [2:0] cycle = 0; /* Cycle for instructions. */
`INSN_stack_HL: wdata <= registers[`REG_L];
endcase
end
- 2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+ 2: begin /* Twiddle thumbs. */ end
3: begin
`EXEC_NEWCYCLE;
`EXEC_INC_PC;
endcase
end
end
+ `INSN_ALU_A: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
`INSN_NOP: begin
`EXEC_NEWCYCLE;
`EXEC_INC_PC;
end
endcase
end
- `INSN_RET: begin
+ `INSN_RET,`INSN_RETCC: begin
case (cycle)
0: begin
rd <= 1;
address <= {registers[`REG_SPH],registers[`REG_SPL]};
end
- 1: begin
+ 1: begin // SPECIAL CASE: cycle does NOT increase linearly with ret!
+ `EXEC_INC_PC; // cycle 1 is skipped if we are not retcc
+ case (opcode[4:3])
+ `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ endcase
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]};
+ end
+ 2: begin
rd <= 1;
address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
end
- 2: begin /* twiddle thumbs */ end
- 3: begin
+ 3: begin /* twiddle thumbs */ end
+ 4: begin
`EXEC_NEWCYCLE;
// do NOT increment PC!
end
endcase
end
- `INSN_CALL: begin
+ `INSN_CALL,`INSN_CALLCC: begin
case (cycle)
0: begin
`EXEC_INC_PC;
end
2: begin
`EXEC_INC_PC;
+ if (!opcode[0]) // i.e., is callcc
+ /* We need to check the condition code to bail out. */
+ case (opcode[4:3])
+ `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ endcase
end
3: begin
address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
rd <= 1;
end
2: begin
+ `EXEC_INC_PC;
if (!opcode[0]) begin // i.e., JP cc,nn
/* We need to check the condition code to bail out. */
case (opcode[4:3])
`INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
- `INSN_cc_Z: if (!registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
`INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
- `INSN_cc_C: if (!registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
endcase
end
end
end
endcase
end
+ `INSN_JP_HL: begin
+ `EXEC_NEWCYCLE;
+ end
+ `INSN_JR_imm,`INSN_JRCC_imm: begin
+ case (cycle)
+ 0: begin
+ `EXEC_INC_PC;
+ `EXEC_NEXTADDR_PCINC;
+ rd <= 1;
+ end
+ 1: begin
+ `EXEC_INC_PC;
+ if (opcode[5]) begin // i.e., JP cc,nn
+ /* We need to check the condition code to bail out. */
+ case (opcode[4:3])
+ `INSN_cc_NZ: if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_Z: if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_NC: if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ `INSN_cc_C: if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+ endcase
+ end
+ end
+ 2: begin
+ `EXEC_NEWCYCLE;
+ end
+ endcase
+ end
+ `INSN_INCDEC16: begin
+ case (cycle)
+ 0: begin
+ case (opcode[5:4])
+ `INSN_reg16_BC: begin
+ tmp <= registers[`REG_B];
+ tmp2 <= registers[`REG_C];
+ end
+ `INSN_reg16_DE: begin
+ tmp <= registers[`REG_D];
+ tmp2 <= registers[`REG_E];
+ end
+ `INSN_reg16_HL: begin
+ tmp <= registers[`REG_H];
+ tmp2 <= registers[`REG_L];
+ end
+ `INSN_reg16_SP: begin
+ tmp <= registers[`REG_SPH];
+ tmp2 <= registers[`REG_SPL];
+ end
+ endcase
+ end
+ 1: begin
+ `EXEC_INC_PC;
+ `EXEC_NEWCYCLE;
+ end
+ endcase
+ end
default:
$stop;
endcase
registers[`REG_F][3:0]
};
end
+ `INSN_alu_SUB: begin
+ registers[`REG_A] <=
+ registers[`REG_A] - tmp;
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b1,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
+ `INSN_alu_SBC: begin
+ registers[`REG_A] <=
+ registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b1,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
`INSN_alu_AND: begin
registers[`REG_A] <=
registers[`REG_A] & tmp;
registers[`REG_F][3:0]
};
end
+ `INSN_alu_CP: begin
+ registers[`REG_F] <=
+ { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
+ /* N */ 1'b1,
+ /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
+ /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
+ registers[`REG_F][3:0]
+ };
+ end
default:
$stop;
endcase
end
end
+ `INSN_ALU_A: begin
+ case(opcode[5:3])
+ `INSN_alu_RLCA: begin
+ registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_RRCA: begin
+ registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_RLA: begin
+ registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_RRA: begin
+ registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
+ end
+ `INSN_alu_CPL: begin
+ registers[`REG_A] <= ~registers[`REG_A];
+ registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
+ end
+ `INSN_alu_SCF: begin
+ registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+ end
+ `INSN_alu_CCF: begin
+ registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
+ end
+ endcase
+ end
`INSN_NOP: begin /* NOP! */ end
`INSN_RST: begin
case (cycle)
{registers[`REG_SPH],registers[`REG_SPL]}-2;
endcase
end
- `INSN_RET: begin
+ `INSN_RET,`INSN_RETCC: begin
case (cycle)
- 0: begin /* type F */ end
- 1: registers[`REG_PCL] <= rdata;
- 2: registers[`REG_PCH] <= rdata;
- 3: begin
+ 0: if (opcode[0]) // i.e., not RETCC
+ cycle <= 1; // Skip cycle 1; it gets incremented on the next round.
+ 1: begin /* Nothing need happen here. */ end
+ 2: registers[`REG_PCL] <= rdata;
+ 3: registers[`REG_PCH] <= rdata;
+ 4: begin
{registers[`REG_SPH],registers[`REG_SPL]} <=
{registers[`REG_SPH],registers[`REG_SPL]} + 2;
- if (opcode[4]) /* RETI */
+ if (opcode[4] && opcode[0]) /* RETI */
ie <= 1;
end
endcase
end
- `INSN_CALL: begin
+ `INSN_CALL,`INSN_CALLCC: begin
case (cycle)
0: begin /* type F */ end
1: tmp <= rdata; // tmp contains newpcl
{tmp2,tmp};
endcase
end
+ `INSN_JP_HL: begin
+ {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {registers[`REG_H],registers[`REG_L]};
+ end
+ `INSN_JR_imm,`INSN_JRCC_imm: begin
+ case (cycle)
+ 0: begin /* type F */ end
+ 1: tmp <= rdata;
+ 2: {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {registers[`REG_PCH],registers[`REG_PCL]} +
+ {tmp[7]?8'hFF:8'h00,tmp};
+ endcase
+ end
+ `INSN_INCDEC16: begin
+ case (cycle)
+ 0: {tmp,tmp2} <= {tmp,tmp2} +
+ (opcode[3] ? 16'hFFFF : 16'h0001);
+ 1: begin
+ case (opcode[5:4])
+ `INSN_reg16_BC: begin
+ registers[`REG_B] <= tmp;
+ registers[`REG_C] <= tmp2;
+ end
+ `INSN_reg16_DE: begin
+ registers[`REG_D] <= tmp;
+ registers[`REG_E] <= tmp2;
+ end
+ `INSN_reg16_HL: begin
+ registers[`REG_H] <= tmp;
+ registers[`REG_L] <= tmp2;
+ end
+ `INSN_reg16_SP: begin
+ registers[`REG_SPH] <= tmp;
+ registers[`REG_SPL] <= tmp2;
+ end
+ endcase
+ end
+ endcase
+ end
default:
$stop;
endcase
git.joshuawise.com / fpgaboy.git / blobdiff