IP

[fpgaboy.git] / Buttons.v

diff --git a/Buttons.v b/Buttons.v
index 4d8a171613ad4a8d703c1dcf95e52496db4bc702..f81060c873ccc36c6ccaf76250238a3bcdeea21f 100644 (file)
--- a/Buttons.v
+++ b/Buttons.v
@@ -1,4 +1,4 @@
-`define ADDR_P1 16'hFF10
+`define ADDR_P1 16'hFF00
 
 /* note: buttons are 'pressed' when the input is high */
 
@@ -20,7 +20,7 @@ module Buttons(
 
        assign data = (rdlatch && (addrlatch == `ADDR_P1)) ? p1 : 8'bzzzzzzzz;
 
-       wire p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) | (p1[5] ? 4'b1111 : ~buttons[7:4]);
+       wire [3:0] p1013 = (p1[4] ? 4'b1111 : ~buttons[3:0]) & (p1[5] ? 4'b1111 : ~buttons[7:4]);
 
        always @ (posedge core_clk) begin
                if(wr) begin