Poke the UART with a stick. ABABABABABABAB
[fpgaboy.git] / System.v
index 53e6257..259656a 100644 (file)
--- a/System.v
+++ b/System.v
@@ -147,14 +147,14 @@ module TestBench();
 //             .wr(wr),
 //             .rd(rd));
 
-//     wire serio;
-//     UART uart(
-//             .addr(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd),
-//             .serial(serio));
+       wire serio;
+       UART uart(
+               .addr(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .serial(serio));
        
 //     Switches sw(
 //             .clk(clk),
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