Split out more insns

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 0f0496eed4200d7e2f98b8ac9a8ffd3e3952608a..f41805ac3c679aeebded8c8d2014f921fe8931c0 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -36,10 +36,19 @@
 `define INSN_NOP                               8'b00000000
 `define INSN_RST                               8'b11xxx111
 `define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
 `define INSN_NOP                               8'b00000000
 `define INSN_RST                               8'b11xxx111
 `define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET

+`define INSN_RETCC                     8'b110xx000

 `define INSN_CALL                              8'b11001101
 `define INSN_CALL                              8'b11001101

+`define INSN_CALLCC                    8'b110xx100     // Not that call/cc.

 `define INSN_JP_imm                    8'b11000011
 `define INSN_JPCC_imm          8'b110xx010
 `define INSN_ALU_A             8'b00xxx111
 `define INSN_JP_imm                    8'b11000011
 `define INSN_JPCC_imm          8'b110xx010
 `define INSN_ALU_A             8'b00xxx111

+`define INSN_JP_HL                     8'b11101001
+`define INSN_JR_imm                    8'b00011000
+`define INSN_JRCC_imm          8'b001xx000
+`define INSN_INCDEC16          8'b00xxx011
+`define INSN_VOP_INTR          8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI                                8'b11110011
+`define INSN_EI                                8'b11111011

 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01
 
 `define INSN_cc_NZ                     2'b00
 `define INSN_cc_Z                              2'b01


@@ -83,10 +92,11 @@ module GBZ80Core(
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,
        input clk,
        output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] busdata,

-       output reg buswr, output reg busrd);
+       output reg buswr, output reg busrd,
+       input irq, input [7:0] jaddr);

        
        

-       reg [1:0] state = 0;                                    /* State within this bus cycle (see STATE_*). */
-       reg [2:0] cycle = 0;                                    /* Cycle for instructions. */
+       reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
+       reg [2:0] cycle;                                        /* Cycle for instructions. */

        
        reg [7:0] registers[11:0];
        
        
        reg [7:0] registers[11:0];
        


@@ -95,14 +105,14 @@ module GBZ80Core(
        reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
        
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */
        reg [7:0] opcode;                               /* Opcode from the current machine cycle. */
        
        reg [7:0] rdata, wdata;         /* Read data from this bus cycle, or write data for the next. */

-       reg rd = 1, wr = 0, newcycle = 1;
+       reg rd, wr, newcycle;

        
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        
        reg [7:0] tmp, tmp2;                    /* Generic temporary regs. */
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        

-       reg ie = 0;
+       reg ie, iedelay;

        
        initial begin
                registers[ 0] <= 0;
        
        initial begin
                registers[ 0] <= 0;


@@ -117,12 +127,19 @@ module GBZ80Core(
                registers[ 9] <= 0;
                registers[10] <= 0;
                registers[11] <= 0;
                registers[ 9] <= 0;
                registers[10] <= 0;
                registers[11] <= 0;

-               ie <= 0;

                rd <= 1;
                wr <= 0;
                newcycle <= 1;
                state <= 0;
                cycle <= 0;
                rd <= 1;
                wr <= 0;
                newcycle <= 1;
                state <= 0;
                cycle <= 0;

+               busrd <= 0;
+               buswr <= 0;
+               busaddress <= 0;
+               ie <= 0;
+               iedelay <= 0;
+               opcode <= 0;
+               state <= `STATE_WRITEBACK;
+               cycle <= 0;

        end
 
        always @(posedge clk)
        end
 
        always @(posedge clk)


@@ -143,7 +160,10 @@ module GBZ80Core(
                end
                `STATE_DECODE: begin
                        if (newcycle) begin
                end
                `STATE_DECODE: begin
                        if (newcycle) begin

-                               opcode <= busdata;
+                               if (ie && irq)
+                                       opcode <= `INSN_VOP_INTR;
+                               else
+                                       opcode <= busdata;

                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;
                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;


@@ -151,6 +171,10 @@ module GBZ80Core(
                                if (rd) rdata <= busdata;
                                cycle <= cycle + 1;
                        end
                                if (rd) rdata <= busdata;
                                cycle <= cycle + 1;
                        end

+                       if (iedelay) begin
+                               ie <= 1;
+                               iedelay <= 0;
+                       end

                        buswr <= 0;
                        busrd <= 0;
                        wr <= 0;
                        buswr <= 0;
                        busrd <= 0;
                        wr <= 0;


@@ -167,213 +191,9 @@ module GBZ80Core(
 `define EXEC_NEWCYCLE \
        newcycle <= 1; rd <= 1; wr <= 0
                        casex (opcode)
 `define EXEC_NEWCYCLE \
        newcycle <= 1; rd <= 1; wr <= 0
                        casex (opcode)

-                       `INSN_LD_reg_imm8: begin
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               `EXEC_INC_PC;
-                                               if (opcode[5:3] == `INSN_reg_dHL) begin
-                                                       address <= {registers[`REG_H], registers[`REG_L]};
-                                                       wdata <= rdata;
-                                                       rd <= 0;
-                                                       wr <= 1;
-                                               end else begin
-                                                       `EXEC_NEWCYCLE;
-                                               end
-                                       end
-                               2:      begin
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_HALT: begin
-                               `EXEC_NEWCYCLE;
-                               /* XXX Interrupts needed for HALT. */
-                       end
-                       `INSN_LD_HL_reg: begin
-                               case (cycle)
-                               0:      begin
-                                               case (opcode[2:0])
-                                               `INSN_reg_A:    wdata <= registers[`REG_A];
-                                               `INSN_reg_B:    wdata <= registers[`REG_B];
-                                               `INSN_reg_C:    wdata <= registers[`REG_C];
-                                               `INSN_reg_D:    wdata <= registers[`REG_D];
-                                               `INSN_reg_E:    wdata <= registers[`REG_E];
-                                               `INSN_reg_H:    wdata <= registers[`REG_H];
-                                               `INSN_reg_L:    wdata <= registers[`REG_L];
-                                               endcase
-                                               address <= {registers[`REG_H], registers[`REG_L]};
-                                               wr <= 1; rd <= 0;
-                                       end
-                               1:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_LD_reg_HL: begin
-                               case(cycle)
-                               0:      begin
-                                               address <= {registers[`REG_H], registers[`REG_L]};
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               tmp <= rdata;
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_LD_reg_reg: begin
-                               `EXEC_INC_PC;
-                               `EXEC_NEWCYCLE;
-                               case (opcode[2:0])
-                               `INSN_reg_A:    tmp <= registers[`REG_A];
-                               `INSN_reg_B:    tmp <= registers[`REG_B];
-                               `INSN_reg_C:    tmp <= registers[`REG_C];
-                               `INSN_reg_D:    tmp <= registers[`REG_D];
-                               `INSN_reg_E:    tmp <= registers[`REG_E];
-                               `INSN_reg_H:    tmp <= registers[`REG_H];
-                               `INSN_reg_L:    tmp <= registers[`REG_L];
-                               endcase
-                       end
-                       `INSN_LD_reg_imm16: begin
-                               `EXEC_INC_PC;
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               2: begin `EXEC_NEWCYCLE; end
-                               endcase
-                       end
-                       `INSN_LD_SP_HL: begin
-                               case (cycle)
-                               0:      begin
-                                               tmp <= registers[`REG_H];
-                                       end
-                               1:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                               tmp <= registers[`REG_L];
-                                       end
-                               endcase
-                       end
-                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
-                               case (cycle)
-                               0:      begin
-                                               wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: wdata <= registers[`REG_A];
-                                               `INSN_stack_BC: wdata <= registers[`REG_B];
-                                               `INSN_stack_DE: wdata <= registers[`REG_D];
-                                               `INSN_stack_HL: wdata <= registers[`REG_H];
-                                               endcase
-                                       end
-                               1:      begin
-                                               wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: wdata <= registers[`REG_F];
-                                               `INSN_stack_BC: wdata <= registers[`REG_C];
-                                               `INSN_stack_DE: wdata <= registers[`REG_E];
-                                               `INSN_stack_HL: wdata <= registers[`REG_L];
-                                               endcase
-                                       end
-                               2:      begin /* TWIDDLE OUR FUCKING THUMBS! */ end
-                               3:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                       end
-                               endcase
-                       end
-                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
-                               case (cycle)
-                               0:      begin
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                                       end
-                               1:      begin
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                                       end
-                               2:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                       end
-                               endcase
-                       end
-                       `INSN_LDH_AC: begin
-                               case (cycle)
-                               0:      begin
-                                               address <= {8'hFF,registers[`REG_C]};
-                                               if (opcode[4]) begin    // LD A,(C)
-                                                       rd <= 1;
-                                               end else begin
-                                                       wr <= 1;
-                                                       wdata <= registers[`REG_A];
-                                               end
-                                       end
-                               1:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                       end
-                               endcase
-                       end
-                       `INSN_LDx_AHL: begin
-                               case (cycle)
-                               0:      begin
-                                               address <= {registers[`REG_H],registers[`REG_L]};
-                                               if (opcode[3]) begin    // LDx A, (HL)
-                                                       rd <= 1;
-                                               end else begin
-                                                       wr <= 1;
-                                                       wdata <= registers[`REG_A];
-                                               end
-                                       end
-                               1:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                       end
-                               endcase
-                       end
-                       `INSN_ALU8: begin
-                               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-                                       // fffffffff fuck your shit, read from (HL) :(
-                                       rd <= 1;
-                                       address <= {registers[`REG_H], registers[`REG_L]};
-                               end else begin
-                                       `EXEC_NEWCYCLE;
-                                       `EXEC_INC_PC;
-                                       case (opcode[2:0])
-                                       `INSN_reg_A:    tmp <= registers[`REG_A];
-                                       `INSN_reg_B:    tmp <= registers[`REG_B];
-                                       `INSN_reg_C:    tmp <= registers[`REG_C];
-                                       `INSN_reg_D:    tmp <= registers[`REG_D];
-                                       `INSN_reg_E:    tmp <= registers[`REG_E];
-                                       `INSN_reg_H:    tmp <= registers[`REG_H];
-                                       `INSN_reg_L:    tmp <= registers[`REG_L];
-                                       `INSN_reg_dHL:  tmp <= rdata;
-                                       endcase
-                               end
-                       end
-                       `INSN_ALU_A: begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                       end
-                       `INSN_NOP: begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                       end
+                       `define EXECUTE
+                       `include "allinsns.v"
+                       `undef EXECUTE

                        `INSN_RST: begin
                                case (cycle)
                                0:      begin
                        `INSN_RST: begin
                                case (cycle)
                                0:      begin


@@ -396,24 +216,35 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

-                       `INSN_RET: begin
+                       `INSN_RET,`INSN_RETCC: begin

                                case (cycle)
                                0:      begin
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end
                                case (cycle)
                                0:      begin
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]};
                                        end

-                               1:      begin
+                               1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
+                                               `EXEC_INC_PC;   // cycle 1 is skipped if we are not retcc
+                                               case (opcode[4:3])
+                                               `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                               `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                               `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                               `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                               endcase
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               2:      begin

                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end
                                                rd <= 1;
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
                                        end

-                               2:      begin /* twiddle thumbs */ end
-                               3:      begin
+                               3:      begin /* twiddle thumbs */ end
+                               4:      begin

                                                `EXEC_NEWCYCLE;
                                                // do NOT increment PC!
                                        end
                                endcase
                        end
                                                `EXEC_NEWCYCLE;
                                                // do NOT increment PC!
                                        end
                                endcase
                        end

-                       `INSN_CALL: begin
+                       `INSN_CALL,`INSN_CALLCC: begin

                                case (cycle)
                                0:      begin
                                                `EXEC_INC_PC;
                                case (cycle)
                                0:      begin
                                                `EXEC_INC_PC;


@@ -427,6 +258,14 @@ module GBZ80Core(
                                        end
                                2:      begin
                                                `EXEC_INC_PC;
                                        end
                                2:      begin
                                                `EXEC_INC_PC;

+                                               if (!opcode[0]) // i.e., is callcc
+                                                       /* We need to check the condition code to bail out. */
+                                                       case (opcode[4:3])
+                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       endcase

                                        end
                                3:      begin
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
                                        end
                                3:      begin
                                                address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;


@@ -472,264 +311,96 @@ module GBZ80Core(
                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

-                       default:
-                               $stop;
-                       endcase
-                       state <= `STATE_WRITEBACK;
-               end
-               `STATE_WRITEBACK: begin
-                       casex (opcode)
-                       `INSN_LD_reg_imm8:
-                               case (cycle)
-                               0:      begin end
-                               1:      case (opcode[5:3])
-                                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; end
-                                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; end
-                                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; end
-                                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; end
-                                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; end
-                                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; end
-                                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; end
-                                       `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end
-                                       endcase
-                               2:      begin end
-                               endcase
-                       `INSN_HALT: begin
-                               /* Nothing needs happen here. */
-                               /* XXX Interrupts needed for HALT. */
-                       end
-                       `INSN_LD_HL_reg: begin
-                               /* Nothing of interest here */
+                       `INSN_JP_HL: begin
+                               `EXEC_NEWCYCLE;

                        end
                        end

-                       `INSN_LD_reg_HL: begin
+                       `INSN_JR_imm,`INSN_JRCC_imm: begin

                                case (cycle)
                                case (cycle)

-                               0:      begin end
-                               1:      begin
-                                               case (opcode[5:3])
-                                               `INSN_reg_A:    registers[`REG_A] <= tmp;
-                                               `INSN_reg_B:    registers[`REG_B] <= tmp;
-                                               `INSN_reg_C:    registers[`REG_C] <= tmp;
-                                               `INSN_reg_D:    registers[`REG_D] <= tmp;
-                                               `INSN_reg_E:    registers[`REG_E] <= tmp;
-                                               `INSN_reg_H:    registers[`REG_H] <= tmp;
-                                               `INSN_reg_L:    registers[`REG_L] <= tmp;
-                                               endcase
+                               0:      begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEXTADDR_PCINC;
+                                               rd <= 1;

                                        end
                                        end

-                               endcase
-                       end
-                       `INSN_LD_reg_reg: begin
-                               case (opcode[5:3])
-                               `INSN_reg_A:    registers[`REG_A] <= tmp;
-                               `INSN_reg_B:    registers[`REG_B] <= tmp;
-                               `INSN_reg_C:    registers[`REG_C] <= tmp;
-                               `INSN_reg_D:    registers[`REG_D] <= tmp;
-                               `INSN_reg_E:    registers[`REG_E] <= tmp;
-                               `INSN_reg_H:    registers[`REG_H] <= tmp;
-                               `INSN_reg_L:    registers[`REG_L] <= tmp;
-                               endcase
-                       end
-                       `INSN_LD_reg_imm16: begin
-                               case (cycle)
-                               0:      begin /* */ end
-                               1:      begin
-                                               case (opcode[5:4])
-                                               `INSN_reg16_BC: registers[`REG_C] <= rdata;
-                                               `INSN_reg16_DE: registers[`REG_E] <= rdata;
-                                               `INSN_reg16_HL: registers[`REG_L] <= rdata;
-                                               `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
-                                               endcase
+                               1: begin
+                                               `EXEC_INC_PC;
+                                               if (opcode[5]) begin    // i.e., JP cc,nn
+                                                       /* We need to check the condition code to bail out. */
+                                                       case (opcode[4:3])
+                                                       `INSN_cc_NZ:    if (registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_Z:             if (~registers[`REG_F][7]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_NC:    if (registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       `INSN_cc_C:             if (~registers[`REG_F][4]) begin `EXEC_NEWCYCLE; end
+                                                       endcase
+                                               end

                                        end
                                        end

-                               2: begin
-                                               case (opcode[5:4])
-                                               `INSN_reg16_BC: registers[`REG_B] <= rdata;
-                                               `INSN_reg16_DE: registers[`REG_D] <= rdata;
-                                               `INSN_reg16_HL: registers[`REG_H] <= rdata;
-                                               `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
-                                               endcase
+                               2:      begin
+                                               `EXEC_NEWCYCLE;

                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

-                       `INSN_LD_SP_HL: begin
-                               case (cycle)
-                               0:      registers[`REG_SPH] <= tmp;
-                               1: registers[`REG_SPL] <= tmp;
-                               endcase
-                       end
-                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
-                               case (cycle)
-                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                               1:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 1;
-                               2:      begin /* type F */ end
-                               3:      begin /* type F */ end
-                               endcase
-                       end
-                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
+                       `INSN_INCDEC16: begin

                                case (cycle)
                                case (cycle)

-                               0:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} + 1;
-                               1:      begin
+                               0: begin

                                                case (opcode[5:4])
                                                case (opcode[5:4])

-                                               `INSN_stack_AF: registers[`REG_F] <= rdata;
-                                               `INSN_stack_BC: registers[`REG_C] <= rdata;
-                                               `INSN_stack_DE: registers[`REG_E] <= rdata;
-                                               `INSN_stack_HL: registers[`REG_L] <= rdata;
+                                               `INSN_reg16_BC: begin
+                                                       tmp <= registers[`REG_B];
+                                                       tmp2 <= registers[`REG_C];
+                                               end
+                                               `INSN_reg16_DE: begin
+                                                       tmp <= registers[`REG_D];
+                                                       tmp2 <= registers[`REG_E];
+                                               end
+                                               `INSN_reg16_HL: begin
+                                                       tmp <= registers[`REG_H];
+                                                       tmp2 <= registers[`REG_L];
+                                               end
+                                               `INSN_reg16_SP: begin
+                                                       tmp <= registers[`REG_SPH];
+                                                       tmp2 <= registers[`REG_SPL];
+                                               end

                                                endcase
                                                endcase

-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 1;

                                        end
                                        end

-                               2:      begin
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: registers[`REG_A] <= rdata;
-                                               `INSN_stack_BC: registers[`REG_B] <= rdata;
-                                               `INSN_stack_DE: registers[`REG_D] <= rdata;
-                                               `INSN_stack_HL: registers[`REG_H] <= rdata;
-                                               endcase
+                               1: begin
+                                               `EXEC_INC_PC;
+                                               `EXEC_NEWCYCLE;

                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

-                       `INSN_LDH_AC: begin
+                       `INSN_VOP_INTR: begin

                                case (cycle)
                                case (cycle)

-                               0:      begin /* Type F */ end
-                               1:      if (opcode[4])
-                                               registers[`REG_A] <= rdata;
-                               endcase
-                       end
-                       `INSN_LDx_AHL: begin
-                               case (cycle)
-                               0:      begin /* Type F */ end
+                               0:      begin
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+                                               wdata <= registers[`REG_PCH];
+                                               wr <= 1;
+                                       end

                                1:      begin
                                1:      begin

-                                               if (opcode[3])
-                                                       registers[`REG_A] <= rdata;
-                                               {registers[`REG_H],registers[`REG_L]} <=
-                                                       opcode[4] ? // if set, LDD, else LDI
-                                                       ({registers[`REG_H],registers[`REG_L]} - 1) :
-                                                       ({registers[`REG_H],registers[`REG_L]} + 1);
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                                               wdata <= registers[`REG_PCL];
+                                               wr <= 1;
+                                       end
+                               2:      begin
+                                               `EXEC_NEWCYCLE;

                                        end
                                endcase
                        end
                                        end
                                endcase
                        end

-                       `INSN_ALU8: begin
-                               if ((opcode[2:0] == `INSN_reg_dHL) && (cycle == 0)) begin
-                                       /* Sit on our asses. */
-                               end else begin          /* Actually do the computation! */
-                                       case (opcode[5:3])
-                                       `INSN_alu_ADD: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] + tmp;
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 1'b0,
-                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_ADC: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 1'b0,
-                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                                         /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_SUB: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] - tmp;
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 1'b1,
-                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_SBC: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]});
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] - (tmp + {7'b0,registers[`REG_F][4]})) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 1'b1,
-                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - ({1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]})) >> 4 == 1) ? 1'b1 : 1'b0,
-                                                         /* C */ (({1'b0,registers[`REG_A]} - ({1'b0,tmp} + {8'b0,registers[`REG_F][4]})) >> 8 == 1) ? 1'b1 : 1'b0,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_AND: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] & tmp;
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
-                                                         3'b010,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_OR: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] | tmp;
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
-                                                         3'b000,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_XOR: begin
-                                               registers[`REG_A] <=
-                                                       registers[`REG_A] ^ tmp;
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
-                                                         3'b000,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       `INSN_alu_CP: begin
-                                               registers[`REG_F] <=
-                                                       { /* Z */ ((registers[`REG_A] - tmp) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 1'b1,
-                                                         /* H */ (({1'b0,registers[`REG_A][3:0]} - {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
-                                                         /* C */ (({1'b0,registers[`REG_A]} - {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
-                                                         registers[`REG_F][3:0]
-                                                       };
-                                       end
-                                       default:
-                                               $stop;
-                                       endcase
-                               end
+                       `INSN_DI: begin
+                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC;

                        end
                        end

-                       `INSN_ALU_A: begin
-                               case(opcode[5:3])
-                               `INSN_alu_RLCA: begin
-                                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_A][7]};
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
-                               end
-                               `INSN_alu_RRCA: begin
-                                       registers[`REG_A] <= {registers[`REG_A][0],registers[`REG_A][7:1]};
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
-                               end
-                               `INSN_alu_RLA: begin
-                                       registers[`REG_A] <= {registers[`REG_A][6:0],registers[`REG_F][4]};
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][7],registers[`REG_F][3:0]};
-                               end
-                               `INSN_alu_RRA: begin
-                                       registers[`REG_A] <= {registers[`REG_A][4],registers[`REG_A][7:1]};
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],registers[`REG_A][0],registers[`REG_F][3:0]};
-                               end
-                               `INSN_alu_CPL: begin
-                                       registers[`REG_A] <= ~registers[`REG_A];
-                                       registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
-                               end
-                               `INSN_alu_SCF: begin
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
-                               end
-                               `INSN_alu_CCF: begin
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
-                               end
-                               endcase
+                       `INSN_EI: begin
+                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC;

                        end
                        end

-                       `INSN_NOP: begin /* NOP! */ end
+                       default:
+                               $stop;
+                       endcase
+                       state <= `STATE_WRITEBACK;
+               end
+               `STATE_WRITEBACK: begin
+                       casex (opcode)
+                       `define WRITEBACK
+                       `include "allinsns.v"
+                       `undef WRITEBACK

                        `INSN_RST: begin
                                case (cycle)
                                0:      begin /* type F */ end
                        `INSN_RST: begin
                                case (cycle)
                                0:      begin /* type F */ end


@@ -739,20 +410,22 @@ module GBZ80Core(
                                                {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                endcase
                        end
                                                {registers[`REG_SPH],registers[`REG_SPL]}-2;
                                endcase
                        end

-                       `INSN_RET: begin
+                       `INSN_RET,`INSN_RETCC: begin

                                case (cycle)
                                case (cycle)

-                               0:      begin /* type F */ end
-                               1:      registers[`REG_PCL] <= rdata;
-                               2:      registers[`REG_PCH] <= rdata;
-                               3:      begin
+                               0:      if (opcode[0])  // i.e., not RETCC
+                                               cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
+                               1: begin /* Nothing need happen here. */ end
+                               2:      registers[`REG_PCL] <= rdata;
+                               3:      registers[`REG_PCH] <= rdata;
+                               4:      begin

                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 2;
                                                {registers[`REG_SPH],registers[`REG_SPL]} <=
                                                        {registers[`REG_SPH],registers[`REG_SPL]} + 2;

-                                               if (opcode[4])  /* RETI */
+                                               if (opcode[4] && opcode[0])     /* RETI */

                                                        ie <= 1;
                                        end
                                endcase
                        end
                                                        ie <= 1;
                                        end
                                endcase
                        end

-                       `INSN_CALL: begin
+                       `INSN_CALL,`INSN_CALLCC: begin

                                case (cycle)
                                0:      begin /* type F */ end
                                1:      tmp <= rdata;   // tmp contains newpcl
                                case (cycle)
                                0:      begin /* type F */ end
                                1:      tmp <= rdata;   // tmp contains newpcl


@@ -775,6 +448,60 @@ module GBZ80Core(
                                                {tmp2,tmp};
                                endcase
                        end
                                                {tmp2,tmp};
                                endcase
                        end

+                       `INSN_JP_HL: begin
+                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                       {registers[`REG_H],registers[`REG_L]};
+                       end
+                       `INSN_JR_imm,`INSN_JRCC_imm: begin
+                               case (cycle)
+                               0:      begin /* type F */ end
+                               1:      tmp <= rdata;
+                               2: {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                               {registers[`REG_PCH],registers[`REG_PCL]} +
+                                               {tmp[7]?8'hFF:8'h00,tmp};
+                               endcase
+                       end
+                       `INSN_INCDEC16: begin
+                               case (cycle)
+                               0:      {tmp,tmp2} <= {tmp,tmp2} +
+                                               (opcode[3] ? 16'hFFFF : 16'h0001);
+                               1: begin
+                                               case (opcode[5:4])
+                                               `INSN_reg16_BC: begin
+                                                       registers[`REG_B] <= tmp;
+                                                       registers[`REG_C] <= tmp2;
+                                               end
+                                               `INSN_reg16_DE: begin
+                                                       registers[`REG_D] <= tmp;
+                                                       registers[`REG_E] <= tmp2;
+                                               end
+                                               `INSN_reg16_HL: begin
+                                                       registers[`REG_H] <= tmp;
+                                                       registers[`REG_L] <= tmp2;
+                                               end
+                                               `INSN_reg16_SP: begin
+                                                       registers[`REG_SPH] <= tmp;
+                                                       registers[`REG_SPL] <= tmp2;
+                                               end
+                                               endcase
+                                       end
+                               endcase
+                       end
+                       `INSN_VOP_INTR: begin
+                               case (cycle)
+                               0:      begin end
+                               1:      begin end
+                               2:      begin
+                                               ie <= 0;
+                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                                       {8'b0,jaddr};
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+                                       end
+                               endcase
+                       end
+                       `INSN_DI: ie <= 0;
+                       `INSN_EI: iedelay <= 1;

                        default:
                                $stop;
                        endcase
                        default:
                                $stop;
                        endcase