]> Joshua Wise's Git repositories - fpgaboy.git/blobdiff - GBZ80Core.v
git.joshuawise.com / fpgaboy.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Start refactoring instructions.
[fpgaboy.git] / GBZ80Core.v
diff --git a/GBZ80Core.v b/GBZ80Core.v
index ae6ff0076d3676591d162f1b6a1eb5b903b83087..b53a6e20ec07a736baa0452c971e2d060c5ea8e2 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -191,151 +191,9 @@ module GBZ80Core(
 `define EXEC_NEWCYCLE \
        newcycle <= 1; rd <= 1; wr <= 0
                        casex (opcode)
 `define EXEC_NEWCYCLE \
        newcycle <= 1; rd <= 1; wr <= 0
                        casex (opcode)
-                       `INSN_LD_reg_imm8: begin
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               `EXEC_INC_PC;
-                                               if (opcode[5:3] == `INSN_reg_dHL) begin
-                                                       address <= {registers[`REG_H], registers[`REG_L]};
-                                                       wdata <= rdata;
-                                                       rd <= 0;
-                                                       wr <= 1;
-                                               end else begin
-                                                       `EXEC_NEWCYCLE;
-                                               end
-                                       end
-                               2:      begin
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_HALT: begin
-                               `EXEC_NEWCYCLE;
-                               /* XXX Interrupts needed for HALT. */
-                       end
-                       `INSN_LD_HL_reg: begin
-                               case (cycle)
-                               0:      begin
-                                               case (opcode[2:0])
-                                               `INSN_reg_A:    wdata <= registers[`REG_A];
-                                               `INSN_reg_B:    wdata <= registers[`REG_B];
-                                               `INSN_reg_C:    wdata <= registers[`REG_C];
-                                               `INSN_reg_D:    wdata <= registers[`REG_D];
-                                               `INSN_reg_E:    wdata <= registers[`REG_E];
-                                               `INSN_reg_H:    wdata <= registers[`REG_H];
-                                               `INSN_reg_L:    wdata <= registers[`REG_L];
-                                               endcase
-                                               address <= {registers[`REG_H], registers[`REG_L]};
-                                               wr <= 1; rd <= 0;
-                                       end
-                               1:      begin
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_LD_reg_HL: begin
-                               case(cycle)
-                               0:      begin
-                                               address <= {registers[`REG_H], registers[`REG_L]};
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               tmp <= rdata;
-                                               `EXEC_INC_PC;
-                                               `EXEC_NEWCYCLE;
-                                       end
-                               endcase
-                       end
-                       `INSN_LD_reg_reg: begin
-                               `EXEC_INC_PC;
-                               `EXEC_NEWCYCLE;
-                               case (opcode[2:0])
-                               `INSN_reg_A:    tmp <= registers[`REG_A];
-                               `INSN_reg_B:    tmp <= registers[`REG_B];
-                               `INSN_reg_C:    tmp <= registers[`REG_C];
-                               `INSN_reg_D:    tmp <= registers[`REG_D];
-                               `INSN_reg_E:    tmp <= registers[`REG_E];
-                               `INSN_reg_H:    tmp <= registers[`REG_H];
-                               `INSN_reg_L:    tmp <= registers[`REG_L];
-                               endcase
-                       end
-                       `INSN_LD_reg_imm16: begin
-                               `EXEC_INC_PC;
-                               case (cycle)
-                               0:      begin
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               1:      begin
-                                               `EXEC_NEXTADDR_PCINC;
-                                               rd <= 1;
-                                       end
-                               2: begin `EXEC_NEWCYCLE; end
-                               endcase
-                       end
-                       `INSN_LD_SP_HL: begin
-                               case (cycle)
-                               0:      begin
-                                               tmp <= registers[`REG_H];
-                                       end
-                               1:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                               tmp <= registers[`REG_L];
-                                       end
-                               endcase
-                       end
-                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
-                               case (cycle)
-                               0:      begin
-                                               wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: wdata <= registers[`REG_A];
-                                               `INSN_stack_BC: wdata <= registers[`REG_B];
-                                               `INSN_stack_DE: wdata <= registers[`REG_D];
-                                               `INSN_stack_HL: wdata <= registers[`REG_H];
-                                               endcase
-                                       end
-                               1:      begin
-                                               wr <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: wdata <= registers[`REG_F];
-                                               `INSN_stack_BC: wdata <= registers[`REG_C];
-                                               `INSN_stack_DE: wdata <= registers[`REG_E];
-                                               `INSN_stack_HL: wdata <= registers[`REG_L];
-                                               endcase
-                                       end
-                               2:      begin /* Twiddle thumbs. */ end
-                               3:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                       end
-                               endcase
-                       end
-                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
-                               case (cycle)
-                               0:      begin
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                                       end
-                               1:      begin
-                                               rd <= 1;
-                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
-                                       end
-                               2:      begin
-                                               `EXEC_NEWCYCLE;
-                                               `EXEC_INC_PC;
-                                       end
-                               endcase
-                       end
+                       `define EXECUTE
+                       `include "allinsns.v"
+                       `undef EXECUTE
                        `INSN_LDH_AC: begin
                                case (cycle)
                                0:      begin
                        `INSN_LDH_AC: begin
                                case (cycle)
                                0:      begin
@@ -602,114 +460,9 @@ module GBZ80Core(
                end
                `STATE_WRITEBACK: begin
                        casex (opcode)
                end
                `STATE_WRITEBACK: begin
                        casex (opcode)
-                       `INSN_LD_reg_imm8:
-                               case (cycle)
-                               0:      begin end
-                               1:      case (opcode[5:3])
-                                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; end
-                                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; end
-                                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; end
-                                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; end
-                                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; end
-                                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; end
-                                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; end
-                                       `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end
-                                       endcase
-                               2:      begin end
-                               endcase
-                       `INSN_HALT: begin
-                               /* Nothing needs happen here. */
-                               /* XXX Interrupts needed for HALT. */
-                       end
-                       `INSN_LD_HL_reg: begin
-                               /* Nothing of interest here */
-                       end
-                       `INSN_LD_reg_HL: begin
-                               case (cycle)
-                               0:      begin end
-                               1:      begin
-                                               case (opcode[5:3])
-                                               `INSN_reg_A:    registers[`REG_A] <= tmp;
-                                               `INSN_reg_B:    registers[`REG_B] <= tmp;
-                                               `INSN_reg_C:    registers[`REG_C] <= tmp;
-                                               `INSN_reg_D:    registers[`REG_D] <= tmp;
-                                               `INSN_reg_E:    registers[`REG_E] <= tmp;
-                                               `INSN_reg_H:    registers[`REG_H] <= tmp;
-                                               `INSN_reg_L:    registers[`REG_L] <= tmp;
-                                               endcase
-                                       end
-                               endcase
-                       end
-                       `INSN_LD_reg_reg: begin
-                               case (opcode[5:3])
-                               `INSN_reg_A:    registers[`REG_A] <= tmp;
-                               `INSN_reg_B:    registers[`REG_B] <= tmp;
-                               `INSN_reg_C:    registers[`REG_C] <= tmp;
-                               `INSN_reg_D:    registers[`REG_D] <= tmp;
-                               `INSN_reg_E:    registers[`REG_E] <= tmp;
-                               `INSN_reg_H:    registers[`REG_H] <= tmp;
-                               `INSN_reg_L:    registers[`REG_L] <= tmp;
-                               endcase
-                       end
-                       `INSN_LD_reg_imm16: begin
-                               case (cycle)
-                               0:      begin /* */ end
-                               1:      begin
-                                               case (opcode[5:4])
-                                               `INSN_reg16_BC: registers[`REG_C] <= rdata;
-                                               `INSN_reg16_DE: registers[`REG_E] <= rdata;
-                                               `INSN_reg16_HL: registers[`REG_L] <= rdata;
-                                               `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
-                                               endcase
-                                       end
-                               2: begin
-                                               case (opcode[5:4])
-                                               `INSN_reg16_BC: registers[`REG_B] <= rdata;
-                                               `INSN_reg16_DE: registers[`REG_D] <= rdata;
-                                               `INSN_reg16_HL: registers[`REG_H] <= rdata;
-                                               `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
-                                               endcase
-                                       end
-                               endcase
-                       end
-                       `INSN_LD_SP_HL: begin
-                               case (cycle)
-                               0:      registers[`REG_SPH] <= tmp;
-                               1: registers[`REG_SPL] <= tmp;
-                               endcase
-                       end
-                       `INSN_PUSH_reg: begin   /* PUSH is 16 cycles! */
-                               case (cycle)
-                               0:      begin /* type F */ end
-                               1:      begin /* type F */ end
-                               2:      begin /* type F */ end
-                               3:      {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                               {registers[`REG_SPH],registers[`REG_SPL]} - 2;
-                               endcase
-                       end
-                       `INSN_POP_reg: begin    /* POP is 12 cycles! */
-                               case (cycle)
-                               0:      begin end
-                               1:      begin
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: registers[`REG_F] <= rdata;
-                                               `INSN_stack_BC: registers[`REG_C] <= rdata;
-                                               `INSN_stack_DE: registers[`REG_E] <= rdata;
-                                               `INSN_stack_HL: registers[`REG_L] <= rdata;
-                                               endcase
-                                       end
-                               2:      begin
-                                               case (opcode[5:4])
-                                               `INSN_stack_AF: registers[`REG_A] <= rdata;
-                                               `INSN_stack_BC: registers[`REG_B] <= rdata;
-                                               `INSN_stack_DE: registers[`REG_D] <= rdata;
-                                               `INSN_stack_HL: registers[`REG_H] <= rdata;
-                                               endcase
-                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
-                                       end
-                               endcase
-                       end
+                       `define WRITEBACK
+                       `include "allinsns.v"
+                       `undef WRITEBACK
                        `INSN_LDH_AC: begin
                                case (cycle)
                                0:      begin /* Type F */ end
                        `INSN_LDH_AC: begin
                                case (cycle)
                                0:      begin /* Type F */ end
@@ -843,7 +596,7 @@ module GBZ80Core(
                                        registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
                                end
                                `INSN_alu_SCF: begin
                                        registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
                                end
                                `INSN_alu_SCF: begin
-                                       registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+                                       registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]};
                                end
                                `INSN_alu_CCF: begin
                                        registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
                                end
                                `INSN_alu_CCF: begin
                                        registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
Partial Nintendo GameBoy / GBZ80 implementation on a Xilinx FPGA
This page took 0.03519 seconds and 4 git commands to generate.