registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
end
`INSN_alu_SCF: begin
- registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]};
end
`INSN_alu_CCF: begin
registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};