Working RAM :D

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 8fc4c9ca7d5ac8ed490cf86e6cb7214af0dd8046..dec02b8bfadc766aa96bc76aa6130be9ca82936c 100644 (file)
--- a/System.v
+++ b/System.v
@@ -21,19 +21,22 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
-       reg [7:0] ram [8191:0];
+       // synthesis attribute ram_style of reg is block
+       reg [7:0] ram [2047:0];
        
-       wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
+       wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        always @(negedge clk)
        begin
-               if (decode && rd)
-                       odata <= ram[address[12:0]];
-               else if (decode && wr)
-                       ram[address[12:0]] <= data;
+               if (decode)
+               begin
+                       if (wr)
+                               ram[address[10:0]] <= data;
+                       odata <= ram[address[10:0]];
+               end
        end
 endmodule
 
@@ -61,6 +64,7 @@ endmodule
 module CoreTop(
        input xtal,
        input [7:0] switches,
+       input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
@@ -93,7 +97,8 @@ module CoreTop(
     .addr(addr), 
     .clk(clk), 
     .digit(digits), 
-    .out(seven)
+    .out(seven),
+        .freeze(buttons[0])
     );
         
        Switches sw(