IP

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 84b33b78315fd2e623d52b769e39c3e00d0579de..ec6223624d4b6c4325c63b46d13f5bab4c0f5cd5 100644 (file)
--- a/System.v
+++ b/System.v
@@ -243,6 +243,7 @@ module CoreTop(
        inout [15:0] cr_DQ,
        input ps2c, ps2d,
        output txp, txm,
+       input rxp, rxm,
 `endif
        output wire hs, vs,
        output wire [2:0] r, g,
@@ -483,7 +484,10 @@ module CoreTop(
                .addr(addr[0]),
                .data(data[0]),
                .ethclk(ethclk),
+               .rxclk(xtalb),
                .txp(txp),
-               .txm(txm));
+               .txm(txm),
+               .rxp(rxp),
+               .rxm(rxm));
 `endif
 endmodule