output wire [3:0] digits,
output wire [7:0] seven);
- wire clk;
- //IBUFG ibuf (.O(clk), .I(iclk));
-
+ wire clk;
CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
wire [15:0] addr;
.switches(switches)
);
- UART nouart (
+ UART nouart ( /* no u */
.clk(clk),
.wr(wr),
.rd(rd),
.clk(clk),
.wr(wr),
.rd(rd));
+
+ wire irq, tmrirq;
+ wire [7:0] jaddr;
+ Timer tmr(
+ .clk(clk),
+ .wr(wr),
+ .rd(rd),
+ .addr(addr),
+ .data(data),
+ .irq(tmrirq));
+
+ Interrupt intr(
+ .clk(clk),
+ .rd(rd),
+ .wr(wr),
+ .addr(addr),
+ .data(data),
+ .vblank(0),
+ .lcdc(0),
+ .tovf(tmrirq),
+ .serial(0),
+ .buttons(0),
+ .master(irq),
+ .jaddr(jaddr));
endmodule
module TestBench();
.rd(rd),
.serial(serio));
+ wire irq, tmrirq;
+ wire [7:0] jaddr;
+ Timer tmr(
+ .clk(clk),
+ .wr(wr),
+ .rd(rd),
+ .addr(addr),
+ .data(data),
+ .irq(tmrirq));
+
+ Interrupt intr(
+ .clk(clk),
+ .rd(rd),
+ .wr(wr),
+ .addr(addr),
+ .data(data),
+ .vblank(0),
+ .lcdc(0),
+ .tovf(tmrirq),
+ .serial(0),
+ .buttons(0),
+ .master(irq),
+ .jaddr(jaddr));
+
// Switches sw(
// .clk(clk),
// .address(addr),