RAM needs to be writable, I guess

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 37ca872bdecb246d1e34f40394c565039b2eaff2..02b424cf54b03a366359019648aff429c90243e7 100644 (file)
--- a/System.v
+++ b/System.v
@@ -114,7 +114,7 @@ module CellularRAM(
        reg [8:0] rombank = 1;
        
        assign cr_nOE = decode ? ~rdlatch : 1;
-       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0))) ? ~wrlatch : 1;
+       assign cr_nWE = (decode && ((addrlatch == ADDR_PROGDATA) || (mbc_emul[6:0] == 0) || (addrlatch[15:13] == 3'b101))) ? ~wrlatch : 1;
        
        assign cr_DQ = (~cr_nOE) ? 16'bzzzzzzzzzzzzzzzz : {8'b0, datalatch};
        assign cr_A = (addrlatch[15:14] == 2'b00) ? /* extrom, home bank */ {9'b0,addrlatch[13:0]} :