ALU8IMM

[fpgaboy.git] / insn_ld_reg_imm8.v

diff --git a/insn_ld_reg_imm8.v b/insn_ld_reg_imm8.v
index 77768e0b29a94f232e19ab07a300821aa4c5f440..73404217ca77a4b8d35d0d2357db4222dc29c4e3 100644 (file)
--- a/insn_ld_reg_imm8.v
+++ b/insn_ld_reg_imm8.v
@@ -2,24 +2,17 @@
        `INSN_LD_reg_imm8: begin
                case (cycle)
                0:      begin
-                               `EXEC_INC_PC;
-                               `EXEC_NEXTADDR_PCINC;
-                               rd <= 1;
+                               `EXEC_INC_PC
+                               `EXEC_READ(`_PC + 1)
                        end
                1:      begin
-                               `EXEC_INC_PC;
-                               if (opcode[5:3] == `INSN_reg_dHL) begin
-                                       address <= {registers[`REG_H], registers[`REG_L]};
-                                       wdata <= rdata;
-                                       rd <= 0;
-                                       wr <= 1;
-                               end else begin
-                                       `EXEC_NEWCYCLE;
-                               end
-                       end
-               2:      begin
-                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC
+                               if (opcode[5:3] == `INSN_reg_dHL)
+                                       `EXEC_WRITE(`_HL, rdata)
+                               else
+                                       `EXEC_NEWCYCLE
                        end
+               2:      `EXEC_NEWCYCLE
                endcase
        end
 `endif
@@ -29,13 +22,13 @@
                case (cycle)
                0:      begin end
                1:      case (opcode[5:3])
-                       `INSN_reg_A:    begin registers[`REG_A] <= rdata; end
-                       `INSN_reg_B:    begin registers[`REG_B] <= rdata; end
-                       `INSN_reg_C:    begin registers[`REG_C] <= rdata; end
-                       `INSN_reg_D:    begin registers[`REG_D] <= rdata; end
-                       `INSN_reg_E:    begin registers[`REG_E] <= rdata; end
-                       `INSN_reg_H:    begin registers[`REG_H] <= rdata; end
-                       `INSN_reg_L:    begin registers[`REG_L] <= rdata; end
+                       `INSN_reg_A:    begin `_A <= rdata; end
+                       `INSN_reg_B:    begin `_B <= rdata; end
+                       `INSN_reg_C:    begin `_C <= rdata; end
+                       `INSN_reg_D:    begin `_D <= rdata; end
+                       `INSN_reg_E:    begin `_E <= rdata; end
+                       `INSN_reg_H:    begin `_H <= rdata; end
+                       `INSN_reg_L:    begin `_L <= rdata; end
                        `INSN_reg_dHL:  begin /* Go off to cycle 2 */ end
                        endcase
                2:      begin end