Clean up some warnings.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index b53a6e20ec07a736baa0452c971e2d060c5ea8e2..d556cd50cd5eb81cc1398616df0418bdc7f34390 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -90,9 +90,9 @@
 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,

-       output reg [15:0] busaddress = 0,       /* BUS_* is latched on STATE_FETCH. */
+       output reg [15:0] busaddress,   /* BUS_* is latched on STATE_FETCH. */

        inout [7:0] busdata,
        inout [7:0] busdata,

-       output reg buswr = 0, output reg busrd = 0,
+       output reg buswr, output reg busrd,

        input irq, input [7:0] jaddr);
        
        reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
        input irq, input [7:0] jaddr);
        
        reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */


@@ -112,7 +112,7 @@ module GBZ80Core(
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        

-       reg ie = 0, iedelay = 0;
+       reg ie, iedelay;

        
        initial begin
                registers[ 0] <= 0;
        
        initial begin
                registers[ 0] <= 0;