Flop the clock polarity of the LCDC around.

[fpgaboy.git] / insn_ld_hl_reg.v

diff --git a/insn_ld_hl_reg.v b/insn_ld_hl_reg.v
index 0b984311a6500df77a4ccca6883256b81da636b1..fdf3d9ba0a27a7a17416503ef03f6d67d9a2f8e6 100644 (file)
--- a/insn_ld_hl_reg.v
+++ b/insn_ld_hl_reg.v
@@ -3,20 +3,20 @@
                case (cycle)
                0:      begin
                                case (opcode[2:0])
-                               `INSN_reg_A:    wdata <= registers[`REG_A];
-                               `INSN_reg_B:    wdata <= registers[`REG_B];
-                               `INSN_reg_C:    wdata <= registers[`REG_C];
-                               `INSN_reg_D:    wdata <= registers[`REG_D];
-                               `INSN_reg_E:    wdata <= registers[`REG_E];
-                               `INSN_reg_H:    wdata <= registers[`REG_H];
-                               `INSN_reg_L:    wdata <= registers[`REG_L];
+                               `INSN_reg_A:    wdata <= `_A;
+                               `INSN_reg_B:    wdata <= `_B;
+                               `INSN_reg_C:    wdata <= `_C;
+                               `INSN_reg_D:    wdata <= `_D;
+                               `INSN_reg_E:    wdata <= `_E;
+                               `INSN_reg_H:    wdata <= `_H;
+                               `INSN_reg_L:    wdata <= `_L;
                                endcase
-                               address <= {registers[`REG_H], registers[`REG_L]};
+                               address <= `_HL;
                                wr <= 1; rd <= 0;
                        end
                1:      begin
-                               `EXEC_INC_PC;
-                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC
+                               `EXEC_NEWCYCLE
                        end
                endcase
        end