Semi-working, but prone to anus, keyboard driver

[fpgaboy.git] / insn_ld_reg_hl.v

diff --git a/insn_ld_reg_hl.v b/insn_ld_reg_hl.v
index 3fc7862a5d428c452ad4359d2c9688bab93549c0..e420f2ff37b35c7746f9484dff431bb5b716321f 100644 (file)
--- a/insn_ld_reg_hl.v
+++ b/insn_ld_reg_hl.v
@@ -1,14 +1,10 @@
 `ifdef EXECUTE
        `INSN_LD_reg_HL: begin
                case(cycle)
 `ifdef EXECUTE
        `INSN_LD_reg_HL: begin
                case(cycle)

-               0:      begin
-                               address <= {registers[`REG_H], registers[`REG_L]};
-                               rd <= 1;
-                       end
+               0:      `EXEC_READ(`_HL)

                1:      begin
                1:      begin

-                               tmp <= rdata;
-                               `EXEC_INC_PC;
-                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC
+                               `EXEC_NEWCYCLE

                        end
                endcase
        end
                        end
                endcase
        end


@@ -18,17 +14,15 @@
        `INSN_LD_reg_HL: begin
                case (cycle)
                0:      begin end
        `INSN_LD_reg_HL: begin
                case (cycle)
                0:      begin end

-               1:      begin
-                               case (opcode[5:3])
-                               `INSN_reg_A:    registers[`REG_A] <= tmp;
-                               `INSN_reg_B:    registers[`REG_B] <= tmp;
-                               `INSN_reg_C:    registers[`REG_C] <= tmp;
-                               `INSN_reg_D:    registers[`REG_D] <= tmp;
-                               `INSN_reg_E:    registers[`REG_E] <= tmp;
-                               `INSN_reg_H:    registers[`REG_H] <= tmp;
-                               `INSN_reg_L:    registers[`REG_L] <= tmp;
-                               endcase
-                       end
+               1:      case (opcode[5:3])
+                       `INSN_reg_A:    `_A <= rdata;
+                       `INSN_reg_B:    `_B <= rdata;
+                       `INSN_reg_C:    `_C <= rdata;
+                       `INSN_reg_D:    `_D <= rdata;
+                       `INSN_reg_E:    `_E <= rdata;
+                       `INSN_reg_H:    `_H <= rdata;
+                       `INSN_reg_L:    `_L <= rdata;
+                       endcase

                endcase
        end
 `endif
                endcase
        end
 `endif