Add cut 1 of a cellram module

[fpgaboy.git] / insn_ld_sp_hl.v

diff --git a/insn_ld_sp_hl.v b/insn_ld_sp_hl.v
index ba10d5af0b7f33a76c6c79b28fdc59f5df7166ae..3d4fc1846ba54dca0b1003534c6beb14e17e9f66 100644 (file)
--- a/insn_ld_sp_hl.v
+++ b/insn_ld_sp_hl.v
@@ -1,13 +1,11 @@
 `ifdef EXECUTE
        `INSN_LD_SP_HL: begin
                case (cycle)
-               0:      begin
-                               tmp <= registers[`REG_H];
-                       end
+               0:      tmp <= `_H;
                1:      begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
-                               tmp <= registers[`REG_L];
+                               `EXEC_NEWCYCLE
+                               `EXEC_INC_PC
+                               tmp <= `_L;
                        end
                endcase
        end
@@ -16,8 +14,8 @@
 `ifdef WRITEBACK
        `INSN_LD_SP_HL: begin
                case (cycle)
-               0:      registers[`REG_SPH] <= tmp;
-               1:      registers[`REG_SPL] <= tmp;
+               0:      `_SPH <= tmp;
+               1:      `_SPL <= tmp;
                endcase
        end
 `endif