Rework it all to use the new macros.

[fpgaboy.git] / insn_pop_reg.v

diff --git a/insn_pop_reg.v b/insn_pop_reg.v
index 9d4acbda9eb70f9e437bec5bba59440b1d06e55a..5a7da08fcf6fb4cefe31fe26d5a48947089a45c9 100644 (file)
--- a/insn_pop_reg.v
+++ b/insn_pop_reg.v
@@ -1,17 +1,11 @@
 `ifdef EXECUTE
        `INSN_POP_reg: begin    /* POP is 12 cycles! */
                case (cycle)
-               0:      begin
-                               rd <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
-                       end
-               1:      begin
-                               rd <= 1;
-                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
-                       end
+               0:      `EXEC_READ(`_SP)
+               1:      `EXEC_READ(`_SP + 1)
                2:      begin
-                               `EXEC_NEWCYCLE;
-                               `EXEC_INC_PC;
+                               `EXEC_NEWCYCLE
+                               `EXEC_INC_PC
                        end
                endcase
        end
@@ -23,21 +17,20 @@
                0:      begin end
                1:      begin
                                case (opcode[5:4])
-                               `INSN_stack_AF: registers[`REG_F] <= rdata;
-                               `INSN_stack_BC: registers[`REG_C] <= rdata;
-                               `INSN_stack_DE: registers[`REG_E] <= rdata;
-                               `INSN_stack_HL: registers[`REG_L] <= rdata;
+                               `INSN_stack_AF: `_F <= rdata;
+                               `INSN_stack_BC: `_C <= rdata;
+                               `INSN_stack_DE: `_E <= rdata;
+                               `INSN_stack_HL: `_L <= rdata;
                                endcase
                        end
                2:      begin
                                case (opcode[5:4])
-                               `INSN_stack_AF: registers[`REG_A] <= rdata;
-                               `INSN_stack_BC: registers[`REG_B] <= rdata;
-                               `INSN_stack_DE: registers[`REG_D] <= rdata;
-                               `INSN_stack_HL: registers[`REG_H] <= rdata;
+                               `INSN_stack_AF: `_A <= rdata;
+                               `INSN_stack_BC: `_B <= rdata;
+                               `INSN_stack_DE: `_D <= rdata;
+                               `INSN_stack_HL: `_H <= rdata;
                                endcase
-                               {registers[`REG_SPH],registers[`REG_SPL]} <=
-                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+                               `_SP <= `_SP + 2;
                        end
                endcase
        end