Add a dirty hack to make the sim pipe directly to the readout script.

[fpgaboy.git] / insn_ld_reg_imm16.v

diff --git a/insn_ld_reg_imm16.v b/insn_ld_reg_imm16.v
index b9bd84e369d50d5f2207eabe77e8f1e28dbc2fc3..cf79aaab948f94e9d8727efb383df5144f30481f 100644 (file)
--- a/insn_ld_reg_imm16.v
+++ b/insn_ld_reg_imm16.v
@@ -1,16 +1,10 @@
 `ifdef EXECUTE
        `INSN_LD_reg_imm16: begin
-               `EXEC_INC_PC;
+               `EXEC_INC_PC
                case (cycle)
-               0:      begin
-                               `EXEC_NEXTADDR_PCINC;
-                               rd <= 1;
-                       end
-               1:      begin
-                               `EXEC_NEXTADDR_PCINC;
-                               rd <= 1;
-                       end
-               2:      begin `EXEC_NEWCYCLE; end
+               0:      `EXEC_READ(`_PC + 1)
+               1:      `EXEC_READ(`_PC + 1)
+               2:      `EXEC_NEWCYCLE
                endcase
        end
 `endif
@@ -21,18 +15,18 @@
                0:      begin /* */ end
                1:      begin
                                case (opcode[5:4])
-                               `INSN_reg16_BC: registers[`REG_C] <= rdata;
-                               `INSN_reg16_DE: registers[`REG_E] <= rdata;
-                               `INSN_reg16_HL: registers[`REG_L] <= rdata;
-                               `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
+                               `INSN_reg16_BC: `_C <= rdata;
+                               `INSN_reg16_DE: `_E <= rdata;
+                               `INSN_reg16_HL: `_L <= rdata;
+                               `INSN_reg16_SP: `_SPL <= rdata;
                                endcase
                        end
                2:      begin
                                case (opcode[5:4])
-                               `INSN_reg16_BC: registers[`REG_B] <= rdata;
-                               `INSN_reg16_DE: registers[`REG_D] <= rdata;
-                               `INSN_reg16_HL: registers[`REG_H] <= rdata;
-                               `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
+                               `INSN_reg16_BC: `_B <= rdata;
+                               `INSN_reg16_DE: `_D <= rdata;
+                               `INSN_reg16_HL: `_H <= rdata;
+                               `INSN_reg16_SP: `_SPH <= rdata;
                                endcase
                        end
                endcase