Fix the UART, and set it to 19k2 for more stable operation. Make the downloader a...

[fpgaboy.git] / diag.asm

diff --git a/diag.asm b/diag.asm
index 50cefe73b0dff3747ce10de9d9d98202859e9b01..780f5c2b452df06e5da55f2c4d1d9cb932058dfb 100644 (file)
--- a/diag.asm
+++ b/diag.asm
@@ -1,6 +1,3 @@
-       section "end",HOME[1024]
-       nop
-
        SECTION "a",HOME[$00]
 
 start: jp main
@@ -14,6 +11,19 @@ start: jp main
        section "tmro",HOME[$50]
        jp tmro
 
+       SECTION "b",HOME[$100]
+boot:  jr main         ; $0100
+       nop             ; $0102
+       nop             ; $0103
+       ;Nintendo Logo  ; $0104
+       DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D 
+       DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99 
+       DB $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E
+       ;$0134 
+       DB $00,$E7,$00,$00,$00,$00,$00,$00, $00,$00,$00,$00,$00,$00,$00,$00
+       ;$0144
+       DB $00,$00,$00,$00,$00,$00,$00,$00, $00,$00,$00,$00,$00,$00,$00,$00
+
 main:
        ld a, $FF
        ld c, $51
@@ -33,6 +43,9 @@ main:
        ld hl, signon
        call puts
 
+       ld a, $91
+       ld [$FF40], a
+
        call putscreen
        
        ei
@@ -50,59 +63,69 @@ main:
 signon:
        db $0D,$0A,$1B,"[1mFPGABoy Diagnostic ROM",$1B,"[0m",$0D,$0A,0
 
+tiles:
+       db %01111100
+       db %11000110
+       db %11000110
+       db %11111110
+       db %11000110
+       db %11000110
+       db %11000110
+       db %00000000
+       
+       db %11111100
+       db %11000110
+       db %11000110
+       db %11111100
+       db %11000110
+       db %11000110
+       db %11111100
+       db %00000000
+
+       db %01111100
+       db %11000110
+       db %11000010
+       db %11000000
+       db %11000010
+       db %11000110
+       db %01111100
+       db %00000000
+
+       db %11111100
+       db %11000110
+       db %11000110
+       db %11000110
+       db %11000110
+       db %11000110
+       db %11111100
+       db %00000000
+
 putscreen:
+       LD A,$fc                ; $001d  Setup BG palette
+       LD [$FF47],A    ; $001f
+
        ; Wait for vblank
        call .vblwait
 
        ld hl, $8000    ; Copy two tiles.
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
-       ld [hli], a
-       ld [hli], a
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
-       ld [hli], a
-       ld [hli], a
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
-       ld [hli], a
-       ld [hli], a
-       ld a, $AA
-       ld [hli], a
-       ld [hli], a
-       ld a, $55
+       ld de, tiles
+       ld c, $20
+.cloop:        ld a, [de]
+       inc de
        ld [hli], a
        ld [hli], a
+       dec c
        xor a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
-       ld [hli], a
+       cp c
+       jr nz, .cloop
        
        ld hl, $9800
 .vloop:        call .vblwait
        ld c, $40
-.loop: ld a, $01
-       ld [hli], a
-       xor a
+       ld b, 0
+.loop: ld a, b
+       inc b
+       and $03
        ld [hli], a
        ld a, h
        cp $9C
@@ -134,30 +157,19 @@ vbl:
        ld [$FF0F], a
 
        ld a, [$FF51]
-       ld b, a
-       and $80
-       cp $80
-       jr nz, .nothing
-       ld c, $0
+       bit 7, a
+       jr z, .nothing
 
-       ld a, b
-       and $1
-       cp c
+       bit 0, a
        call nz, .scyup
        
-       ld a, b
-       and $2
-       cp c
+       bit 1, a
        call nz, .scydown
        
-       ld a, b
-       and $4
-       cp c
+       bit 2, a
        call nz, .scxup
        
-       ld a, b
-       and $8
-       cp c
+       bit 3, a
        call nz, .scxdown
 
 .nothing:
@@ -319,8 +331,8 @@ waitsw:
        ld a,[c]
        cp $0
        jr z,.loop1
-.loop2:
-       ld a,[c]
+
+.loop2:        ld a,[c]
        cp $0
        jr nz,.loop2
        ret