JP

[fpgaboy.git] / Uart.v

diff --git a/Uart.v b/Uart.v
index f8ee27bc47997d4be5666903466cdedec6329fee..a036c64e5ad7858422f27515730da6d13c15c9d0 100644 (file)
--- a/Uart.v
+++ b/Uart.v
@@ -8,8 +8,13 @@ module UART(
        input wr,
        input rd,
        input [15:0] addr,
-       input [7:0] data,
+       inout [7:0] data,
        output reg serial);
+       
+       wire decode = (addr == `MMAP_ADDR);
+       
+       wire [7:0] odata;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 
        reg [7:0] data_stor = 0;
        reg [15:0] clkdiv = 0;
@@ -17,7 +22,9 @@ module UART(
        reg data_end = 0;
        reg [3:0] diqing = 4'b0000;
        
-       wire new = (wr) && (!have_data) && (addr == `MMAP_ADDR);
+       wire new = (wr) && (!have_data) && decode;
+       
+       assign odata = have_data ? 8'b1 : 8'b0;
 
        always @ (negedge clk)
        begin