Add an interrupt ack, so that interrupts are cleared automatically. This fixes APOCAL...

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index e1aa3087b0a94f4cb7e422c3160b7849bf334c5a..29aab5203b4c24c909f6cfab270ffc9b0ecbeaff 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -152,7 +152,7 @@ module GBZ80Core(
        inout [15:0] bus1address,       /* BUS_* is latched on STATE_FETCH. */
        inout [7:0] bus1data,
        inout bus1wr, bus1rd,
-       input irq, input [7:0] jaddr,
+       input irq, output reg irqack, input [7:0] jaddr,
        output reg [1:0] state);
 
 //     reg [1:0] state;                                        /* State within this bus cycle (see STATE_*). */
@@ -282,6 +282,7 @@ module GBZ80Core(
                cycle <= 0;
                twobyte <= 0;
                bootstrap_enb <= 1;
+               irqack <= 0;
        end
 
        always @(negedge clk)   /* Set things up at the negedge to prepare for the posedge. */
@@ -295,8 +296,11 @@ module GBZ80Core(
                                busaddress <= address;
                                buswr <= wr;
                                busrd <= rd;
-                               if (wr)
+                               if (wr) begin
                                        buswdata <= wdata;
+                                       if (address == 16'hFF50)
+                                               bootstrap_enb <= 0;
+                               end
                        end
                end
                `STATE_DECODE: begin    /* Make sure this only happens for one clock. */
@@ -338,8 +342,10 @@ module GBZ80Core(
                        state <= `STATE_EXECUTE;
                end
                `STATE_EXECUTE: begin
+               `ifdef isim
                        if (opcode[7:0] === 8'bxxxxxxxx)
                                $stop;
+               `endif
                        casex (opcode)
                        `define EXECUTE
                        `include "allinsns.v"