reg rdlatch = 0;
reg [7:0] addrlatch = 0;
- reg [7:0] brom [255:0];
- initial $readmemh("bootstrap.hex", brom);
+ reg romno = 0, romnotmp = 0;
+ reg [7:0] brom0 [255:0];
+ reg [7:0] brom1 [255:0];
+
+ initial $readmemh("fpgaboot.hex", brom0);
+ initial $readmemh("gbboot.hex", brom1);
wire decode = address[15:8] == 0;
- wire [7:0] odata = brom[addrlatch];
+ wire [7:0] odata = (romno == 0) ? brom0[addrlatch] : brom1[addrlatch];
always @(posedge clk) begin
rdlatch <= rd && decode;
addrlatch <= address[7:0];
+ if (wr && decode) romnotmp <= data[0];
+ if (rd && address == 16'h0000) romno <= romnotmp; /* Latch when the program restarts. */
end
assign data = rdlatch ? odata : 8'bzzzzzzzz;
endmodule