Move the core to core/

[fpgaboy.git] / core / insn_ret-retcc.v

diff --git a/core/insn_ret-retcc.v b/core/insn_ret-retcc.v
new file mode 100644 (file)
index 0000000..dab27c3
--- /dev/null
+++ b/core/insn_ret-retcc.v
@@ -0,0 +1,37 @@
+`ifdef EXECUTE
+       `INSN_RET,`INSN_RETCC: begin
+               case (cycle)
+               0:      `EXEC_READ(`_SP)
+               1:      begin   // SPECIAL CASE: cycle does NOT increase linearly with ret!
+                               `EXEC_INC_PC    // cycle 1 is skipped if we are not retcc
+                               case (opcode[4:3])
+                               `INSN_cc_NZ:    if (`_F[7])  `EXEC_NEWCYCLE
+                               `INSN_cc_Z:     if (~`_F[7]) `EXEC_NEWCYCLE
+                               `INSN_cc_NC:    if (`_F[4])  `EXEC_NEWCYCLE
+                               `INSN_cc_C:     if (~`_F[4]) `EXEC_NEWCYCLE
+                               endcase
+                               `EXEC_READ(`_SP)        // retry the read
+                       end
+               2:      `EXEC_READ(`_SP + 1)
+               3:      begin /* twiddle thumbs */ end
+               4:      `EXEC_NEWCYCLE
+               endcase
+       end
+`endif
+
+`ifdef WRITEBACK
+       `INSN_RET,`INSN_RETCC: begin
+               case (cycle)
+               0:      if (opcode[0])  // i.e., not RETCC
+                               cycle <= 1;     // Skip cycle 1; it gets incremented on the next round.
+               1:      begin /* Nothing need happen here. */ end
+               2:      `_PCL <= rdata;
+               3:      `_PCH <= rdata;
+               4:      begin
+                               `_SP <= `_SP + 2;
+                               if (opcode[4] && opcode[0])     /* RETI */
+                                       ie <= 1;
+                       end
+               endcase
+       end
+`endif