Add some verilator and isim compatibility

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 05c449ac5981f33d84b1095433821e70e3368182..1182b327709e7d4cd3fc24e52fd2a128cd46d1c1 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -130,8 +130,19 @@
 `define EXEC_NEXTADDR_PCINC    address <= `_PC + 1;
 `define EXEC_NEWCYCLE          begin newcycle <= 1; rd <= 1; wr <= 0; end
 `define EXEC_NEWCYCLE_TWOBYTE  begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end
 `define EXEC_NEXTADDR_PCINC    address <= `_PC + 1;
 `define EXEC_NEWCYCLE          begin newcycle <= 1; rd <= 1; wr <= 0; end
 `define EXEC_NEWCYCLE_TWOBYTE  begin newcycle <= 1; rd <= 1; wr <= 0; twobyte <= 1; end

-`define EXEC_WRITE(ad, da)     begin address <= (ad); wdata <= (da); wr <= 1; end end
-`define EXEC_READ(ad)          begin address <= (ad); rd <= 1; end end
+`ifdef verilator
+       `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
+       `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
+`else
+       `ifdef isim
+               `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end
+               `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end
+       `else
+/* Work around XST's retarded bugs :\ */
+               `define EXEC_WRITE(ad, da)      begin address <= (ad); wdata <= (da); wr <= 1; end end
+               `define EXEC_READ(ad)           begin address <= (ad); rd <= 1; end end
+       `endif
+`endif

 
 module GBZ80Core(
        input clk,
 
 module GBZ80Core(
        input clk,


@@ -185,7 +196,7 @@ module GBZ80Core(
                        2'b0,
                        tmp[0]};
 
                        2'b0,
                        tmp[0]};
 

-       assign sla   = {tmp[6:0],0};
+       assign sla   = {tmp[6:0],1'b0};

        assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
                        2'b0,
                        tmp[7]};
        assign slaf  = {(tmp[6:0] == 0 ? 1'b1 : 1'b0),
                        2'b0,
                        tmp[7]};


@@ -194,10 +205,10 @@ module GBZ80Core(
 //     assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
 
        assign swap  = {tmp[3:0],tmp[7:4]};
 //     assign sraf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),2'b0,tmp[0]};   now in assign srlf =
 
        assign swap  = {tmp[3:0],tmp[7:4]};

-       assign swapf = {(tmp == 0 ? 1'b1 : 1'b0),
+       assign swapf = {(tmp == 1'b0 ? 1'b1 : 1'b0),

                        3'b0};
 
                        3'b0};
 

-       assign srl   = {0,tmp[7:1]};
+       assign srl   = {1'b0,tmp[7:1]};

        assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
                        2'b0,
                        tmp[0]};
        assign srlf  = {(tmp[7:1] == 0 ? 1'b1 : 1'b0),
                        2'b0,
                        tmp[0]};


@@ -267,12 +278,12 @@ module GBZ80Core(
                `STATE_DECODE: begin
                        if (newcycle) begin
                                if (twobyte) begin
                `STATE_DECODE: begin
                        if (newcycle) begin
                                if (twobyte) begin

-                                       opcode <= {1,busdata};
+                                       opcode <= {1'b1,busdata};

                                        twobyte <= 0;
                                end else if (ie && irq)
                                        opcode <= `INSN_VOP_INTR;
                                else
                                        twobyte <= 0;
                                end else if (ie && irq)
                                        opcode <= `INSN_VOP_INTR;
                                else

-                                       opcode <= {0,busdata};
+                                       opcode <= {1'b0,busdata};

                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;
                                rdata <= busdata;
                                newcycle <= 0;
                                cycle <= 0;