Add RET/IRET. Fix a bug in RST where the PC pushed to the stack was incorrect.

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 1aaa01c9fce246300e4aa50372055767ff268533..c0c2b26f9712ee16ea2298246e7563343e3ab00a 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -33,6 +33,9 @@
 `define INSN_LDH_AC                    8'b111x0010     // Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL                   8'b001xx010     // LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8                              8'b10xxxxxx     // 10 xxx yyy
+`define INSN_NOP                               8'b00000000
+`define INSN_RST                               8'b11xxx111
+`define INSN_RET                               8'b110x1001     // 1 = RETI, 0 = RET
 
 `define INSN_reg_A             3'b111
 `define INSN_reg_B             3'b000
@@ -82,6 +85,8 @@ module GBZ80Core(
        reg [7:0] buswdata;
        assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
        
+       reg ie = 0;
+       
        initial begin
                registers[ 0] <= 0;
                registers[ 1] <= 0;
@@ -333,6 +338,49 @@ module GBZ80Core(
                                        endcase
                                end
                        end
+                       `INSN_NOP: begin
+                               `EXEC_NEWCYCLE;
+                               `EXEC_INC_PC;
+                       end
+                       `INSN_RST: begin
+                               case (cycle)
+                               0:      begin
+                                               `EXEC_INC_PC;           // This goes FIRST
+                                       end
+                               1: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+                                               wdata <= registers[`REG_PCH];
+                                       end
+                               2: begin
+                                               wr <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                               wdata <= registers[`REG_PCL];
+                                       end
+                               3: begin
+                                               `EXEC_NEWCYCLE;
+                                               {registers[`REG_PCH],registers[`REG_PCL]} <=
+                                                       {10'b0,opcode[5:3],3'b0};
+                                       end
+                               endcase
+                       end
+                       `INSN_RET: begin
+                               case (cycle)
+                               0:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]};
+                                       end
+                               1:      begin
+                                               rd <= 1;
+                                               address <= {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+                                       end
+                               2:      begin /* twiddle thumbs */ end
+                               3:      begin
+                                               `EXEC_NEWCYCLE;
+                                               // do NOT increment PC!
+                                       end
+                               endcase
+                       end
                        default:
                                $stop;
                        endcase
@@ -508,7 +556,7 @@ module GBZ80Core(
                                                        registers[`REG_A] + tmp;
                                                registers[`REG_F] <=
                                                        { /* Z */ ((registers[`REG_A] + tmp) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 0,
+                                                         /* N */ 1'b0,
                                                          /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]}) >> 4 == 1) ? 1'b1 : 1'b0,
                                                          /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp}) >> 8 == 1) ? 1'b1 : 1'b0,
                                                          registers[`REG_F][3:0]
@@ -519,7 +567,7 @@ module GBZ80Core(
                                                        registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]};
                                                registers[`REG_F] <=
                                                        { /* Z */ ((registers[`REG_A] + tmp + {7'b0,registers[`REG_F][4]}) == 0) ? 1'b1 : 1'b0,
-                                                         /* N */ 0,
+                                                         /* N */ 1'b0,
                                                          /* H */ (({1'b0,registers[`REG_A][3:0]} + {1'b0,tmp[3:0]} + {4'b0,registers[`REG_F][4]}) >> 4 == 1) ? 1'b1 : 1'b0,
                                                          /* C */ (({1'b0,registers[`REG_A]} + {1'b0,tmp} + {8'b0,registers[`REG_F][4]}) >> 8 == 1) ? 1'b1 : 1'b0,
                                                          registers[`REG_F][3:0]
@@ -530,7 +578,7 @@ module GBZ80Core(
                                                        registers[`REG_A] & tmp;
                                                registers[`REG_F] <=
                                                        { /* Z */ ((registers[`REG_A] & tmp) == 0) ? 1'b1 : 1'b0,
-                                                         0,1,0,
+                                                         3'b010,
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
@@ -539,7 +587,7 @@ module GBZ80Core(
                                                        registers[`REG_A] | tmp;
                                                registers[`REG_F] <=
                                                        { /* Z */ ((registers[`REG_A] | tmp) == 0) ? 1'b1 : 1'b0,
-                                                         0,0,0,
+                                                         3'b000,
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
@@ -548,7 +596,7 @@ module GBZ80Core(
                                                        registers[`REG_A] ^ tmp;
                                                registers[`REG_F] <=
                                                        { /* Z */ ((registers[`REG_A] ^ tmp) == 0) ? 1'b1 : 1'b0,
-                                                         0,0,0,
+                                                         3'b000,
                                                          registers[`REG_F][3:0]
                                                        };
                                        end
@@ -557,6 +605,39 @@ module GBZ80Core(
                                        endcase
                                end
                        end
+                       `INSN_NOP: begin /* NOP! */ end
+                       `INSN_RST: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      cycle <= 2;
+                               2: cycle <= 3;
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]}-2;
+                                       end
+                               endcase
+                       end
+                       `INSN_RET: begin
+                               case (cycle)
+                               0:      cycle <= 1;
+                               1:      begin
+                                               cycle <= 2;
+                                               registers[`REG_PCL] <= rdata;
+                                       end
+                               2:      begin
+                                               cycle <= 3;
+                                               registers[`REG_PCH] <= rdata;
+                                       end
+                               3:      begin
+                                               cycle <= 0;
+                                               {registers[`REG_SPH],registers[`REG_SPL]} <=
+                                                       {registers[`REG_SPH],registers[`REG_SPL]} + 2;
+                                               if (opcode[4])  /* RETI */
+                                                       ie <= 1;
+                                       end
+                               endcase
+                       end
                        endcase
                        state <= `STATE_FETCH;
                end