Add DI/EI delay test. Add LD M, A.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 40817714e138de5885341d98c866d41634db6805..5b0fb3cc45f05c81f58e96f7263b386e4eaf1619 100644 (file)
--- a/System.v
+++ b/System.v
@@ -72,9 +72,6 @@ module CoreTop(
        wire clk;       
        CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
        
-       wire cclk;
-       IBUFG ibuf (.O(cclk), .I(switches[0]));
-
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
@@ -82,9 +79,9 @@ module CoreTop(
        wire irq, tmrirq;
        wire [7:0] jaddr;
        wire [1:0] state;
-
+       
        GBZ80Core core(
-               .clk(cclk),
+               .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
@@ -107,10 +104,10 @@ module CoreTop(
                .out(seven),
                .freeze(buttons[0]),
                .periods(
-                       (state == 2'b00) ? 4'b1000 :
-                       (state == 2'b01) ? 4'b0100 :
-                       (state == 2'b10) ? 4'b0010 :
-                                          4'b0001) );
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );
         
        Switches sw(
                .address(addr),
@@ -119,7 +116,7 @@ module CoreTop(
                .wr(wr),
                .rd(rd),
                .ledout(leds),
-               .switches({switches[7:1],1'b0})
+               .switches(switches)
                );
 
        UART nouart (   /* no u */
@@ -175,7 +172,7 @@ module TestBench();
        wire [7:0] leds;
        wire [7:0] switches;
        
-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),