Fix insn_bit. HOLY SHIT THE BOOT ROM WORKS c.c

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 40817714e138de5885341d98c866d41634db6805..caa6ae34024a08e6f4444f3f5a264ba762cbfaa2 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,22 +6,45 @@ module ROM(
        input clk,
        input wr, rd);
 
        input clk,
        input wr, rd);
 

-       reg [7:0] rom [2047:0];
+       reg [7:0] rom [1023:0];

        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;

-       wire [7:0] odata = rom[address[11:0]];
+       wire [7:0] odata = rom[address[10:0]];

        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        //assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        //assign data = rd ? odata : 8'bzzzzzzzz;
 endmodule
 

+module MiniRAM(                        /* XXX will need to go INSIDE the CPU for when we do DMA */
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+       
+       reg [7:0] ram [127:0];
+       
+       wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+       reg [7:0] odata;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       
+       always @(negedge clk)
+       begin
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[6:0]] <= data;
+                       odata <= ram[address[6:0]];
+               end
+       end
+endmodule
+

 module InternalRAM(
        input [15:0] address,
        inout [7:0] data,
        input clk,
        input wr, rd);
        
 module InternalRAM(
        input [15:0] address,
        inout [7:0] data,
        input clk,
        input wr, rd);
        

-       // synthesis attribute ram_style of reg is block
+       // synthesis attribute ram_style of ram is block

        reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;


@@ -67,24 +90,26 @@ module CoreTop(
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,

-       output wire [7:0] seven);
+       output wire [7:0] seven,
+       output wire hs, vs,
+       output wire [2:0] r, g,
+       output wire [1:0] b);

        
        

-       wire clk;       
-       CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
+       wire xtalb, clk, vgaclk;
+       IBUFG iclkbuf(.O(xtalb), .I(xtal));
+       CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
+       pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));

        
        

-       wire cclk;
-       IBUFG ibuf (.O(cclk), .I(switches[0]));
-

        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
        
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
        

-       wire irq, tmrirq;
+       wire irq, tmrirq, lcdcirq, vblankirq;

        wire [7:0] jaddr;
        wire [1:0] state;
        wire [7:0] jaddr;
        wire [1:0] state;

-
+       

        GBZ80Core core(
        GBZ80Core core(

-               .clk(cclk),
+               .clk(clk),

                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),


@@ -100,6 +125,39 @@ module CoreTop(
                .wr(wr),
                .rd(rd));
        
                .wr(wr),
                .rd(rd));
        

+       wire lcdhs, lcdvs, lcdclk;
+       wire [2:0] lcdr, lcdg;
+       wire [1:0] lcdb;
+       
+       LCDC lcdc(
+               .addr(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd),
+               .lcdcirq(lcdcirq),
+               .vblankirq(vblankirq),
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb));
+       
+       Framebuffer fb(
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb),
+               .vgaclk(vgaclk),
+               .vgahs(hs),
+               .vgavs(vs),
+               .vgar(r),
+               .vgag(g),
+               .vgab(b));
+       

        AddrMon amon(
                .addr(addr), 
                .clk(clk), 
        AddrMon amon(
                .addr(addr), 
                .clk(clk), 


@@ -107,10 +165,10 @@ module CoreTop(
                .out(seven),
                .freeze(buttons[0]),
                .periods(
                .out(seven),
                .freeze(buttons[0]),
                .periods(

-                       (state == 2'b00) ? 4'b1000 :
-                       (state == 2'b01) ? 4'b0100 :
-                       (state == 2'b10) ? 4'b0010 :
-                                          4'b0001) );
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );

         
        Switches sw(
                .address(addr),
         
        Switches sw(
                .address(addr),


@@ -119,7 +177,7 @@ module CoreTop(
                .wr(wr),
                .rd(rd),
                .ledout(leds),
                .wr(wr),
                .rd(rd),
                .ledout(leds),

-               .switches({switches[7:1],1'b0})
+               .switches(switches)

                );
 
        UART nouart (   /* no u */
                );
 
        UART nouart (   /* no u */


@@ -138,6 +196,14 @@ module CoreTop(
                .wr(wr),
                .rd(rd)
                );
                .wr(wr),
                .rd(rd)
                );

+       
+       MiniRAM mram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd)
+               );

 
        Timer tmr(
                .clk(clk),
 
        Timer tmr(
                .clk(clk),


@@ -154,8 +220,8 @@ module CoreTop(
                .wr(wr),
                .addr(addr),
                .data(data),
                .wr(wr),
                .addr(addr),
                .data(data),

-               .vblank(0),
-               .lcdc(0),
+               .vblank(vblankirq),
+               .lcdc(lcdcirq),

                .tovf(tmrirq),
                .serial(0),
                .buttons(0),
                .tovf(tmrirq),
                .serial(0),
                .buttons(0),


@@ -175,7 +241,7 @@ module TestBench();
        wire [7:0] leds;
        wire [7:0] switches;
        
        wire [7:0] leds;
        wire [7:0] switches;
        

-       always #10 clk <= ~clk;
+       always #62 clk <= ~clk;

        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),