Merge branch 'master' of lu@anyus.res.cmu.edu:/storage/fpga/FPGABoy
[fpgaboy.git] / 7seg.v
diff --git a/7seg.v b/7seg.v
index ba988b0..11e26d4 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -25,7 +25,7 @@ module AddrMon(
                          (dcount == 2'b10) ? periods[2] :
                                              periods[3]) };
 
-       always @ (negedge clk) begin
+       always @ (posedge clk) begin
                if (clkdv == 31) begin
                        clkdv <= 0;
                        dcount <= dcount + 1;
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