and verified

[fpgaboy.git] / 7seg.v

diff --git a/7seg.v b/7seg.v
index ba988b0603de51e22a7cd08d1d71b04a4a6ff3fc..11e26d40848b75e4887ee78c1db6979411c465f9 100644 (file)
--- a/7seg.v
+++ b/7seg.v
@@ -25,7 +25,7 @@ module AddrMon(
                          (dcount == 2'b10) ? periods[2] :
                                              periods[3]) };
 
-       always @ (negedge clk) begin
+       always @ (posedge clk) begin
                if (clkdv == 31) begin
                        clkdv <= 0;
                        dcount <= dcount + 1;