Add ld (bc/de),a, ld a,(bc/de)

[fpgaboy.git] / GBZ80Core.v

diff --git a/GBZ80Core.v b/GBZ80Core.v
index 36cd76af6f6af77895762676654481cac11fc087..3931bddfe007bdfa3584b846bcb0938bd6487e7f 100644 (file)
--- a/GBZ80Core.v
+++ b/GBZ80Core.v
@@ -52,6 +52,7 @@
 `define INSN_LDH_AC            8'b111x0010     // Either LDH A,(C) or LDH (C),A
 `define INSN_LDx_AHL           8'b001xx010     // LDD/LDI A,(HL) / (HL),A
 `define INSN_ALU8              8'b10xxxxxx     // 10 xxx yyy
+`define INSN_ALU8IMM           8'b11xxx110
 `define INSN_NOP               8'b00000000
 `define INSN_RST               8'b11xxx111
 `define INSN_RET               8'b110x1001     // 1 = RETI, 0 = RET
@@ -68,6 +69,11 @@
 `define INSN_VOP_INTR          8'b11111100     // 0xFC is grabbed by the fetch if there is an interrupt pending.
 `define INSN_DI                        8'b11110011
 `define INSN_EI                        8'b11111011
+`define INSN_INCDEC_HL         8'b0011010x
+`define INSN_INCDEC_reg8       8'b00xxx10x
+`define INSN_LD8M_A            8'b111x0000     // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LD16M_A           8'b111x1010     // 1111 for ld A, x; 1110 for ld x, A; bit 1 specifies 16m8 or 8m8
+`define INSN_LDBCDE_A          8'b000xx010     // 0000 for BC, 0001 for DE, 1010 for A,(x), 0010 for (x),A
 
 `define INSN_cc_NZ             2'b00
 `define INSN_cc_Z              2'b01