Yaaay, everything is posedge now

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 40817714e138de5885341d98c866d41634db6805..1872e5125c6324c39a364ce1db44b095393136dc 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,13 +6,53 @@ module ROM(
        input clk,
        input wr, rd);
 
        input clk,
        input wr, rd);
 

-       reg [7:0] rom [2047:0];
+       reg [7:0] odata;
+
+       // synthesis attribute ram_style of rom is block
+       reg [7:0] rom [1023:0];

        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;

-       wire [7:0] odata = rom[address[11:0]];
+       always @(posedge clk)
+               odata <= rom[address[10:0]];
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+endmodule
+
+module BootstrapROM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+
+       reg [7:0] brom [255:0];
+       initial $readmemh("bootstrap.hex", brom);
+
+       wire decode = address[15:8] == 0;
+       wire [7:0] odata = brom[address[7:0]];

        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;

-       //assign data = rd ? odata : 8'bzzzzzzzz;
+endmodule
+
+module MiniRAM(
+       input [15:0] address,
+       inout [7:0] data,
+       input clk,
+       input wr, rd);
+       
+       reg [7:0] ram [127:0];
+       
+       wire decode = (address >= 16'hFF80) && (address <= 16'hFFFE);
+       reg [7:0] odata;
+       assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
+       
+       always @(posedge clk)
+       begin
+               if (decode)     // This has to go this way. The only way XST knows how to do
+               begin                           // block ram is chip select, write enable, and always
+                       if (wr)         // reading. "else if rd" does not cut it ...
+                               ram[address[6:0]] <= data;
+                       odata <= ram[address[6:0]];
+               end
+       end

 endmodule
 
 module InternalRAM(
 endmodule
 
 module InternalRAM(


@@ -21,14 +61,14 @@ module InternalRAM(
        input clk,
        input wr, rd);
        
        input clk,
        input wr, rd);
        

-       // synthesis attribute ram_style of reg is block
+       // synthesis attribute ram_style of ram is block

        reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        reg [7:0] ram [8191:0];
        
        wire decode = address[15:13] == 3'b110;
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        

-       always @(negedge clk)
+       always @(posedge clk)

        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always
        begin
                if (decode)     // This has to go this way. The only way XST knows how to do
                begin                           // block ram is chip select, write enable, and always


@@ -51,7 +91,7 @@ module Switches(
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        
        reg [7:0] odata;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
        

-       always @(negedge clk)
+       always @(posedge clk)

        begin
                if (decode && rd)
                        odata <= switches;
        begin
                if (decode && rd)
                        odata <= switches;


@@ -60,182 +100,193 @@ module Switches(
        end
 endmodule
 
        end
 endmodule
 

+`ifdef isim
+module Dumpable(input [2:0] r, g, input [1:0] b, input hs, vs, vgaclk);
+endmodule
+`endif
+

 module CoreTop(
 module CoreTop(

+`ifdef isim
+       output reg vgaclk = 0,
+       output reg clk = 0,
+`else

        input xtal,
        input [7:0] switches,
        input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
        input xtal,
        input [7:0] switches,
        input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,

-       output wire [7:0] seven);
+       output wire [7:0] seven,
+`endif
+       output wire hs, vs,
+       output wire [2:0] r, g,
+       output wire [1:0] b,
+       output wire soundl, soundr);
+
+`ifdef isim
+       always #62 clk <= ~clk;
+       always #100 vgaclk <= ~vgaclk;

        
        

-       wire clk;       
-       CPUDCM dcm (.CLKIN_IN(xtal), .CLKFX_OUT(clk));
+       Dumpable dump(r,g,b,hs,vs,vgaclk);

        
        

-       wire cclk;
-       IBUFG ibuf (.O(cclk), .I(switches[0]));
+       wire [7:0] leds;
+       wire serio;
+       wire [3:0] digits;
+       wire [7:0] seven;
+       wire [7:0] switches = 8'b0;
+       wire [3:0] buttons = 4'b0;
+`else  
+       wire xtalb, clk, vgaclk;
+       IBUFG iclkbuf(.O(xtalb), .I(xtal));
+       CPUDCM dcm (.CLKIN_IN(xtalb), .CLKFX_OUT(clk));
+       pixDCM pixdcm (.CLKIN_IN(xtalb), .CLKFX_OUT(vgaclk));
+`endif

 
 

-       wire [15:0] addr;       
-       wire [7:0] data;
-       wire wr, rd;
+       wire [15:0] addr [1:0];
+       wire [7:0] data [1:0];
+       wire wr [1:0], rd [1:0];

        
        

-       wire irq, tmrirq;
+       wire irq, tmrirq, lcdcirq, vblankirq;

        wire [7:0] jaddr;
        wire [1:0] state;
        wire [7:0] jaddr;
        wire [1:0] state;

-
+       

        GBZ80Core core(
        GBZ80Core core(

-               .clk(cclk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd),
+               .clk(clk),
+               .bus0address(addr[0]),
+               .bus0data(data[0]),
+               .bus0wr(wr[0]),
+               .bus0rd(rd[0]),
+               .bus1address(addr[1]),
+               .bus1data(data[1]),
+               .bus1wr(wr[1]),
+               .bus1rd(rd[1]),

                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        
                .irq(irq),
                .jaddr(jaddr),
                .state(state));
        

+       BootstrapROM brom(
+               .address(addr[1]),
+               .data(data[1]),
+               .clk(clk),
+               .wr(wr[1]),
+               .rd(rd[1]));
+       

        ROM rom(
        ROM rom(

-               .address(addr),
-               .data(data),
+               .address(addr[0]),
+               .data(data[0]),
+               .clk(clk),
+               .wr(wr[0]),
+               .rd(rd[0]));
+       
+       wire lcdhs, lcdvs, lcdclk;
+       wire [2:0] lcdr, lcdg;
+       wire [1:0] lcdb;
+       
+       LCDC lcdc(

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd));
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .lcdcirq(lcdcirq),
+               .vblankirq(vblankirq),
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb));
+       
+       Framebuffer fb(
+               .lcdclk(lcdclk),
+               .lcdhs(lcdhs),
+               .lcdvs(lcdvs),
+               .lcdr(lcdr),
+               .lcdg(lcdg),
+               .lcdb(lcdb),
+               .vgaclk(vgaclk),
+               .vgahs(hs),
+               .vgavs(vs),
+               .vgar(r),
+               .vgag(g),
+               .vgab(b));

        
        AddrMon amon(
        
        AddrMon amon(

-               .addr(addr), 

                .clk(clk), 
                .clk(clk), 

+               .addr(addr[0]),

                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),
                .periods(
                .digit(digits), 
                .out(seven),
                .freeze(buttons[0]),
                .periods(

-                       (state == 2'b00) ? 4'b1000 :
-                       (state == 2'b01) ? 4'b0100 :
-                       (state == 2'b10) ? 4'b0010 :
-                                          4'b0001) );
+                       (state == 2'b00) ? 4'b0010 :
+                       (state == 2'b01) ? 4'b0001 :
+                       (state == 2'b10) ? 4'b1000 :
+                                          4'b0100) );

         
        Switches sw(
         
        Switches sw(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .ledout(leds),
                .ledout(leds),

-               .switches({switches[7:1],1'b0})
+               .switches(switches)

                );
 
        UART nouart (   /* no u */
                );
 
        UART nouart (   /* no u */

-               .clk(clk), 
-               .wr(wr), 
-               .rd(rd), 
-               .addr(addr), 
-               .data(data), 
+               .clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),

                .serial(serio)
                );
 
        InternalRAM ram(
                .serial(serio)
                );
 
        InternalRAM ram(

-               .address(addr),
-               .data(data),

                .clk(clk),
                .clk(clk),

-               .wr(wr),
-               .rd(rd)
-               );
-
-       Timer tmr(
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .addr(addr),
-               .data(data),
-               .irq(tmrirq)
+               .address(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0])

                );
        
                );
        

-       Interrupt intr(
+       MiniRAM mram(

                .clk(clk),
                .clk(clk),

-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
-               .vblank(0),
-               .lcdc(0),
-               .tovf(tmrirq),
-               .serial(0),
-               .buttons(0),
-               .master(irq),
-               .jaddr(jaddr));
-endmodule
-
-module TestBench();
-       reg clk = 1;
-       wire [15:0] addr;
-       wire [7:0] data;
-       wire wr, rd;
-       
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
-       
-       wire [7:0] leds;
-       wire [7:0] switches;
-       
-       always #10 clk <= ~clk;
-       GBZ80Core core(
-               .clk(clk),
-               .busaddress(addr),
-               .busdata(data),
-               .buswr(wr),
-               .busrd(rd),
-               .irq(irq),
-               .jaddr(jaddr));
-       
-       ROM rom(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd));
-       
-       InternalRAM ram(
-               .address(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd));
+               .address(addr[1]),
+               .data(data[1]),
+               .wr(wr[1]),
+               .rd(rd[1])
+               );

 
 

-       wire serio;
-       UART uart(
-               .addr(addr),
-               .data(data),
-               .clk(clk),
-               .wr(wr),
-               .rd(rd),
-               .serial(serio));
-       

        Timer tmr(
                .clk(clk),
        Timer tmr(
                .clk(clk),

-               .wr(wr),
-               .rd(rd),
-               .addr(addr),
-               .data(data),
-               .irq(tmrirq));
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .irq(tmrirq)
+               );

        
        Interrupt intr(
                .clk(clk),
        
        Interrupt intr(
                .clk(clk),

-               .rd(rd),
-               .wr(wr),
-               .addr(addr),
-               .data(data),
-               .vblank(0),
-               .lcdc(0),
+               .addr(addr[0]),
+               .data(data[0]),
+               .wr(wr[0]),
+               .rd(rd[0]),
+               .vblank(vblankirq),
+               .lcdc(lcdcirq),

                .tovf(tmrirq),
                .tovf(tmrirq),

-               .serial(0),
-               .buttons(0),
+               .serial(1'b0),
+               .buttons(1'b0),

                .master(irq),
                .jaddr(jaddr));
        
                .master(irq),
                .jaddr(jaddr));
        

-       Switches sw(
-               .clk(clk),
-               .address(addr),
-               .data(data),
-               .wr(wr),
-               .rd(rd),
-               .switches(switches),
-               .ledout(leds));
+       Soundcore sound(
+               .core_clk(clk),
+               .addr(addr[0]),
+               .data(data[0]),
+               .rd(rd[0]),
+               .wr(wr[0]),
+               .snd_data_l(soundl),
+               .snd_data_r(soundr));

 endmodule
 endmodule