Latest shit, I can't remember

[fpgaboy.git] / Soundcore.v

diff --git a/Soundcore.v b/Soundcore.v
index 172ed4f6aee9fc297e6eaf23abff0df929243dca..70c4db1f5dab5794196e02bf7bb3f97690d93ad7 100644 (file)
--- a/Soundcore.v
+++ b/Soundcore.v
@@ -12,29 +12,41 @@ module Soundcore(
        output reg snd_data_r
        );
 
-       reg [7:0] nr50,nr51,nr52;
-       reg [3:0] pwmcnt;
-       reg [4:0] cntclk;
+       reg [7:0] nr50 = 8'h00, nr51 = 8'h00, nr52 = 8'hF0;
+       reg [3:0] pwmcnt = 4'b0000;
+       reg [4:0] cntclk = 5'b00000;
        reg [13:0] lenclk;
        wire [3:0] sndout1,sndout2,sndout3,sndout4;
-       wire [3:0] right_snd = nr51[0] ? sndout1 : 4'b0;
-       wire [3:0] left_snd = nr51[4] ? sndout1 : 4'b0;
-
+       wire [3:0] right_snd =
+               (nr51[0] ? sndout1 : 4'b0) +
+               (nr51[1] ? sndout2 : 4'b0) +
+               (nr51[2] ? sndout3 : 4'b0) +
+               (nr51[3] ? sndout4 : 4'b0);
+       wire [3:0] left_snd =
+               (nr51[4] ? sndout1 : 4'b0) +
+               (nr51[5] ? sndout2 : 4'b0) +
+               (nr51[6] ? sndout3 : 4'b0) +
+               (nr51[7] ? sndout4 : 4'b0);
        assign sndout3 = 0;
        assign sndout4 = 0;
-
-       assign data = rd ?
-                        addr == `ADDR_NR50 ? nr50 :
-                        addr == `ADDR_NR51 ? nr51 :
-                        addr == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
+       
+       reg rdlatch;
+       reg [15:0] addrlatch;
+       
+       assign data = rdlatch ?
+                        addrlatch == `ADDR_NR50 ? nr50 :
+                        addrlatch == `ADDR_NR51 ? nr51 :
+                        addrlatch == `ADDR_NR52 ? nr52 : 8'bzzzzzzzz
                      : 8'bzzzzzzzz;
 
-       always @ (negedge core_clk) begin
+       always @ (posedge core_clk) begin
+               rdlatch <= rd;
+               addrlatch <= addr;
                if(wr) begin
                        case(addr)
                        `ADDR_NR50: nr50 <= data;
                        `ADDR_NR51: nr51 <= data;
-                       `ADDR_NR52: nr52 <= {data[7],3'b1,data[3:0]};
+                       `ADDR_NR52: nr52 <= {data[7],7'b1111111};
                        endcase
                end
                cntclk <= cntclk + 1;
@@ -44,7 +56,7 @@ module Soundcore(
                snd_data_r <= (pwmcnt <= right_snd) ? 1 : 0;
        end
 
-       Sound1(
+       Sound1 s1(
                .core_clk(core_clk),
                .wr(wr),
                .rd(rd),
@@ -52,11 +64,11 @@ module Soundcore(
                .data(data),
                .cntclk(cntclk[4]),
                .lenclk(lenclk[13]),
-               .en(nr52[7] & nr52[0]),
+               .en(nr52[7]),
                .snd_data(sndout1)
        );
        
-       Sound2(
+       Sound2 s2(
                .core_clk(core_clk),
                .wr(wr),
                .rd(rd),
@@ -64,7 +76,7 @@ module Soundcore(
                .data(data),
                .cntclk(cntclk[4]),
                .lenclk(lenclk[13]),
-               .en(nr52[7] & nr52[0]),
+               .en(nr52[7]),
                .snd_data(sndout2)
        );