IP

[fpgaboy.git] / Timer.v

diff --git a/Timer.v b/Timer.v
index e46b38bbaf937d7366c8fdb903ff84a0ce6ddeeb..facf20fe97584400ebff54f35095491806f2b2d2 100644 (file)
--- a/Timer.v
+++ b/Timer.v
@@ -11,15 +11,17 @@ module Timer(
        inout [7:0] data,
        output reg irq = 0);
 
+       reg rdlatch = 0;
+       reg [15:0] addrlatch = 0;
        reg [7:0] tima = 0, tma = 0, tac = 0, div = 0;
        reg ovf = 0;
        reg [9:0] clkdv = 0;
 
-       wire is_tima = addr == `ADDR_TIMA;
-       wire is_tma  = addr == `ADDR_TMA;
-       wire is_tac  = addr == `ADDR_TAC;
+       wire is_tima = addrlatch == `ADDR_TIMA;
+       wire is_tma  = addrlatch == `ADDR_TMA;
+       wire is_tac  = addrlatch == `ADDR_TAC;
 
-       assign data = rd ?
+       assign data = rdlatch ?
                         is_tima ? tima :
                         is_tma ? tma :
                         is_tac ? tac :
@@ -35,6 +37,9 @@ module Timer(
 
        always @ (posedge clk) 
        begin
+               rdlatch <= rd;
+               addrlatch <= addr;
+               
                if(wr) begin
                        case(addr)
                        `ADDR_DIV: div <= 8'b0;