IP

[fpgaboy.git] / Interrupt.v

diff --git a/Interrupt.v b/Interrupt.v
index fcc396b109769355e31e6105eb82cf4b7429ae75..201c328979d64f8abd8908e8e64c9c4974669102 100644 (file)
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -13,16 +13,20 @@ module Interrupt(
        input serial,
        input buttons,
        output master,
        input serial,
        input buttons,
        output master,

+       input ack,

        output [7:0] jaddr);
 
        wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank};
        reg [7:0] imask = 16'hFFFF;
        reg [7:0] ihold = 8'b0;
        wire [7:0] imasked = ihold & imask;
        output [7:0] jaddr);
 
        wire [7:0] iflag = {3'b0,buttons,serial,tovf,lcdc,vblank};
        reg [7:0] imask = 16'hFFFF;
        reg [7:0] ihold = 8'b0;
        wire [7:0] imasked = ihold & imask;

+       
+       reg rdlatch = 0;
+       reg [15:0] addrlatch = 0;

 
 

-       assign data = rd ?
-                        (addr == `ADDR_IF) ? ihold :
-                        (addr == `ADDR_IE) ? imask :
+       assign data = rdlatch ?
+                        (addrlatch == `ADDR_IF) ? ihold :
+                        (addrlatch == `ADDR_IE) ? imask :

                         8'bzzzzzzzz :
                      8'bzzzzzzzz;
 
                         8'bzzzzzzzz :
                      8'bzzzzzzzz;
 


@@ -42,9 +46,18 @@ module Interrupt(
                        `ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end
                        endcase
                        
                        `ADDR_IE : begin imask <= data; ihold <= ihold | iflag; end
                        endcase
                        

-               end
+               end else if (ack)
+                       ihold <= ihold &
+                               (imasked[0] ? 8'b11111110 :
+                                imasked[1] ? 8'b11111101 :
+                                imasked[2] ? 8'b11111011 :
+                                imasked[3] ? 8'b11110111 :
+                                imasked[4] ? 8'b11101111 :
+                                8'b11111111);

                else
                        ihold <= ihold | iflag;
                else
                        ihold <= ihold | iflag;

+               rdlatch <= rd;
+               addrlatch <= addr;

        end
 
 endmodule
        end
 
 endmodule