Make binwire a little bit more error-resistant

[fpgaboy.git] / Interrupt.v

diff --git a/Interrupt.v b/Interrupt.v
index fcc396b109769355e31e6105eb82cf4b7429ae75..26861462d1d1dc07bf5038aacee714b282667b9e 100644 (file)
--- a/Interrupt.v
+++ b/Interrupt.v
@@ -19,10 +19,13 @@ module Interrupt(
        reg [7:0] imask = 16'hFFFF;
        reg [7:0] ihold = 8'b0;
        wire [7:0] imasked = ihold & imask;
+       
+       reg rdlatch = 0;
+       reg [15:0] addrlatch = 0;
 
-       assign data = rd ?
-                        (addr == `ADDR_IF) ? ihold :
-                        (addr == `ADDR_IE) ? imask :
+       assign data = rdlatch ?
+                        (addrlatch == `ADDR_IF) ? ihold :
+                        (addrlatch == `ADDR_IE) ? imask :
                         8'bzzzzzzzz :
                      8'bzzzzzzzz;
 
@@ -45,6 +48,8 @@ module Interrupt(
                end
                else
                        ihold <= ihold | iflag;
+               rdlatch <= rd;
+               addrlatch <= addr;
        end
 
 endmodule