reg [3:0] snd_out = 0;
assign snd_data = en ? snd_out : 0;
+
+ reg rdlatch;
+ reg [15:0] addrlatch;
- assign data = rd ?
- addr == `ADDR_NR21 ? nr21 :
- addr == `ADDR_NR22 ? nr22 :
- addr == `ADDR_NR23 ? nr23 :
- addr == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
+ assign data = rdlatch ?
+ addrlatch == `ADDR_NR21 ? nr21 :
+ addrlatch == `ADDR_NR22 ? nr22 :
+ addrlatch == `ADDR_NR23 ? nr23 :
+ addrlatch == `ADDR_NR24 ? nr24 : 8'bzzzzzzzz
: 8'bzzzzzzzz;
always @ (posedge core_clk) begin
+ rdlatch <= rd;
+ addrlatch <= addr;
if(en && wr) begin
case(addr)
`ADDR_NR21: nr21 <= data;