reg [3:0] delta = 4'b1111;
reg toggle = 0;
reg [3:0] snd_out = 0;
+
+ reg rdlatch;
+ reg [15:0] addrlatch;
assign snd_data = en ? snd_out : 0;
- assign data = rd ?
- addr == `ADDR_NR10 ? nr10 :
- addr == `ADDR_NR11 ? nr11 :
- addr == `ADDR_NR12 ? nr12 :
- addr == `ADDR_NR13 ? nr13 :
- addr == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
+ assign data = rdlatch ?
+ addrlatch == `ADDR_NR10 ? nr10 :
+ addrlatch == `ADDR_NR11 ? nr11 :
+ addrlatch == `ADDR_NR12 ? nr12 :
+ addrlatch == `ADDR_NR13 ? nr13 :
+ addrlatch == `ADDR_NR14 ? nr14 : 8'bzzzzzzzz
: 8'bzzzzzzzz;
always @ (posedge core_clk) begin
+ rdlatch <= rd;
+ addrlatch <= addr;
if(en && wr) begin
case(addr)
`ADDR_NR10: nr10 <= data;