Yaaay, everything is posedge now

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 8f54685cfd33045ea6ad52b80f155b379a17099e..1872e5125c6324c39a364ce1db44b095393136dc 100644 (file)
--- a/System.v
+++ b/System.v
@@ -6,12 +6,15 @@ module ROM(
        input clk,
        input wr, rd);
 
+       reg [7:0] odata;
+
        // synthesis attribute ram_style of rom is block
        reg [7:0] rom [1023:0];
        initial $readmemh("rom.hex", rom);
 
        wire decode = address[15:13] == 0;
-       wire [7:0] odata = rom[address[10:0]];
+       always @(posedge clk)
+               odata <= rom[address[10:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 endmodule
 
@@ -21,11 +24,11 @@ module BootstrapROM(
        input clk,
        input wr, rd);
 
-       reg [7:0] rom [255:0];
-       initial $readmemh("bootstrap.hex", rom);
+       reg [7:0] brom [255:0];
+       initial $readmemh("bootstrap.hex", brom);
 
        wire decode = address[15:8] == 0;
-       wire [7:0] odata = rom[address[7:0]];
+       wire [7:0] odata = brom[address[7:0]];
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
 endmodule