Add files, and add a freezeswitch to debug this issue with push no type check.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 259656abe330f3d4040723c7ed544401573c6c94..033e4b180bca090e52953022b3b5f94b985d9ec0 100644 (file)
--- a/System.v
+++ b/System.v
@@ -23,7 +23,7 @@ module InternalRAM(
        
        reg [7:0] ram [8191:0];
        
-       wire decode = (address >= 16'hC000) && (address < 16'hFE00);
+       wire decode = ({0,address} >= 17'hC000) && ({0,address} < 17'hFE00);
        reg [7:0] odata;
        wire idata = data;
        assign data = (rd && decode) ? odata : 8'bzzzzzzzz;
@@ -61,6 +61,7 @@ endmodule
 module CoreTop(
        input xtal,
        input [7:0] switches,
+       input [3:0] buttons,
        output wire [7:0] leds,
        output serio,
        output wire [3:0] digits,
@@ -93,7 +94,8 @@ module CoreTop(
     .addr(addr), 
     .clk(clk), 
     .digit(digits), 
-    .out(seven)
+    .out(seven),
+        .freeze(buttons[0])
     );
         
        Switches sw(
@@ -114,6 +116,13 @@ module CoreTop(
     .data(data), 
     .serial(serio)
     );
+
+  InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));
 endmodule
 
 module TestBench();
@@ -140,12 +149,12 @@ module TestBench();
                .wr(wr),
                .rd(rd));
        
-//     InternalRAM ram(
-//             .address(addr),
-//             .data(data),
-//             .clk(clk),
-//             .wr(wr),
-//             .rd(rd));
+       InternalRAM ram(
+               .address(addr),
+               .data(data),
+               .clk(clk),
+               .wr(wr),
+               .rd(rd));
 
        wire serio;
        UART uart(