`define INSN_LD_reg_reg 8'b01xxxxxx
`define INSN_LD_reg_imm16 8'b00xx0001
`define INSN_LD_SP_HL 8'b11111001
+`define INSN_PUSH_reg 8'b11xx0101
+`define INSN_POP_reg 8'b11xx0001
+`define INSN_LDH_AC 8'b111x0010 // Either LDH A,(C) or LDH (C),A
`define INSN_reg_A 3'b111
`define INSN_reg_B 3'b000
`define INSN_reg_C 3'b001
`define INSN_reg16_DE 2'b01
`define INSN_reg16_HL 2'b10
`define INSN_reg16_SP 2'b11
+`define INSN_stack_AF 2'b11
+`define INSN_stack_BC 2'b00
+`define INSN_stack_DE 2'b01
+`define INSN_stack_HL 2'b10
module GBZ80Core(
input clk,
output reg [15:0] busaddress, /* BUS_* is latched on STATE_FETCH. */
assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
initial begin
- registers[ 0] = 0;
- registers[ 1] = 0;
- registers[ 2] = 0;
- registers[ 3] = 0;
- registers[ 4] = 0;
- registers[ 5] = 0;
- registers[ 6] = 0;
- registers[ 7] = 0;
- registers[ 8] = 0;
- registers[ 9] = 0;
- registers[10] = 0;
- registers[11] = 0;
+ registers[ 0] <= 0;
+ registers[ 1] <= 0;
+ registers[ 2] <= 0;
+ registers[ 3] <= 0;
+ registers[ 4] <= 0;
+ registers[ 5] <= 0;
+ registers[ 6] <= 0;
+ registers[ 7] <= 0;
+ registers[ 8] <= 0;
+ registers[ 9] <= 0;
+ registers[10] <= 0;
+ registers[11] <= 0;
end
always @(posedge clk)
if (rd) rdata <= busdata;
buswr <= 0;
busrd <= 0;
+ wr <= 0;
+ rd <= 0;
+ address <= 16'bxxxxxxxxxxxxxxxx; // Make it obvious if something of type has happened.
+ wdata <= 8'bxxxxxxxx;
state <= `STATE_EXECUTE;
end
`STATE_EXECUTE: begin
case(cycle)
0: begin
address <= {registers[`REG_H], registers[`REG_L]};
- wr <= 0; rd <= 1;
+ rd <= 1;
end
1: begin
tmp <= rdata;
`INSN_LD_SP_HL: begin
case (cycle)
0: begin
- rd <= 0;
- address <= 16'bxxxxxxxxxxxxxxxx;
tmp <= registers[`REG_H];
end
1: begin
end
endcase
end
+ `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
+ case (cycle)
+ 0: begin
+ wr <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+ case (opcode[5:4])
+ `INSN_stack_AF: wdata <= registers[`REG_A];
+ `INSN_stack_BC: wdata <= registers[`REG_B];
+ `INSN_stack_DE: wdata <= registers[`REG_D];
+ `INSN_stack_HL: wdata <= registers[`REG_H];
+ endcase
+ end
+ 1: begin
+ wr <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
+ case (opcode[5:4])
+ `INSN_stack_AF: wdata <= registers[`REG_F];
+ `INSN_stack_BC: wdata <= registers[`REG_C];
+ `INSN_stack_DE: wdata <= registers[`REG_E];
+ `INSN_stack_HL: wdata <= registers[`REG_L];
+ endcase
+ end
+ 2: begin /* TWIDDLE OUR FUCKING THUMBS! */ end
+ 3: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ endcase
+ end
+ `INSN_POP_reg: begin /* POP is 12 cycles! */
+ case (cycle)
+ 0: begin
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]};
+ end
+ 1: begin
+ rd <= 1;
+ address <= {registers[`REG_SPH],registers[`REG_SPL]};
+ end
+ 2: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ endcase
+ end
+ `INSN_LDH_AC: begin
+ case (cycle)
+ 0: begin
+ address <= {8'hFF,registers[`REG_C]};
+ if (opcode[4]) begin // LD A,(C)
+ rd <= 1;
+ end else begin
+ wr <= 1;
+ wdata <= {8'hFF,registers[`REG_A]};
+ end
+ end
+ 1: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
+ end
+ endcase
+ end
default:
$stop;
endcase
end
endcase
end
+ `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
+ case (cycle)
+ 0: begin
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ cycle <= 1;
+ end
+ 1: begin
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ cycle <= 2;
+ end
+ 2: cycle <= 3;
+ 3: cycle <= 0;
+ endcase
+ end
+ `INSN_POP_reg: begin /* POP is 12 cycles! */
+ case (cycle)
+ 0: begin
+ cycle <= 1;
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+ end
+ 1: begin
+ case (opcode[5:4])
+ `INSN_stack_AF: registers[`REG_F] <= rdata;
+ `INSN_stack_BC: registers[`REG_C] <= rdata;
+ `INSN_stack_DE: registers[`REG_E] <= rdata;
+ `INSN_stack_HL: registers[`REG_L] <= rdata;
+ endcase
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} + 1;
+ cycle <= 2;
+ end
+ 2: begin
+ case (opcode[5:4])
+ `INSN_stack_AF: registers[`REG_A] <= rdata;
+ `INSN_stack_BC: registers[`REG_B] <= rdata;
+ `INSN_stack_DE: registers[`REG_D] <= rdata;
+ `INSN_stack_HL: registers[`REG_H] <= rdata;
+ endcase
+ cycle <= 0;
+ end
+ endcase
+ end
+ `INSN_LDH_AC: begin
+ case (cycle)
+ 0: cycle <= 1;
+ 1: begin
+ cycle <= 0;
+ if (opcode[4])
+ registers[`REG_A] <= rdata;
+ end
+ endcase
+ end
endcase
state <= `STATE_FETCH;
end
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