Some reworks to prepare for transition to makefile. Stack bugfixes.

[fpgaboy.git] / System.v

diff --git a/System.v b/System.v
index 8b8d61344f712e4c39cfae009bf71969f67039a9..5d4fbedf2acadf14bd48a28dfb153570ed63a1cf 100644 (file)
--- a/System.v
+++ b/System.v
@@ -46,7 +46,7 @@ module Switches(
        input clk,
        input wr, rd,
        input [7:0] switches,
-       output reg [7:0] ledout);
+       output reg [7:0] ledout = 0);
        
        wire decode = address == 16'hFF51;
        reg [7:0] odata;
@@ -76,13 +76,18 @@ module CoreTop(
        wire [15:0] addr;       
        wire [7:0] data;
        wire wr, rd;
+       
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
 
        GBZ80Core core(
                .clk(clk),
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .address(addr),
@@ -125,8 +130,6 @@ module CoreTop(
                .wr(wr),
                .rd(rd));
 
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
        Timer tmr(
                .clk(clk),
                .wr(wr),
@@ -156,8 +159,11 @@ module TestBench();
        wire [7:0] data;
        wire wr, rd;
        
-//     wire [7:0] leds;
-//     wire [7:0] switches;
+       wire irq, tmrirq;
+       wire [7:0] jaddr;
+       
+       wire [7:0] leds;
+       wire [7:0] switches;
        
        always #10 clk <= ~clk;
        GBZ80Core core(
@@ -165,7 +171,9 @@ module TestBench();
                .busaddress(addr),
                .busdata(data),
                .buswr(wr),
-               .busrd(rd));
+               .busrd(rd),
+               .irq(irq),
+               .jaddr(jaddr));
        
        ROM rom(
                .clk(clk),
@@ -190,8 +198,6 @@ module TestBench();
                .rd(rd),
                .serial(serio));
        
-       wire irq, tmrirq;
-       wire [7:0] jaddr;
        Timer tmr(
                .clk(clk),
                .wr(wr),
@@ -214,12 +220,12 @@ module TestBench();
                .master(irq),
                .jaddr(jaddr));
        
-//     Switches sw(
-//             .clk(clk),
-//             .address(addr),
-//             .data(data),
-//             .wr(wr),
-//             .rd(rd),
-//             .switches(switches),
-//             .leds(leds));
+       Switches sw(
+               .clk(clk),
+               .address(addr),
+               .data(data),
+               .wr(wr),
+               .rd(rd),
+               .switches(switches),
+               .ledout(leds));
 endmodule