`define INSN_JR_imm 8'b00011000
`define INSN_JRCC_imm 8'b001xx000
`define INSN_INCDEC16 8'b00xxx011
+`define INSN_VOP_INTR 8'b11111100 // 0xFC is grabbed by the fetch if there is an interrupt pending.
+`define INSN_DI 8'b11110011
+`define INSN_EI 8'b11111011
`define INSN_cc_NZ 2'b00
`define INSN_cc_Z 2'b01
input clk,
output reg [15:0] busaddress = 0, /* BUS_* is latched on STATE_FETCH. */
inout [7:0] busdata,
- output reg buswr = 0, output reg busrd = 0);
+ output reg buswr = 0, output reg busrd = 0,
+ input irq, input [7:0] jaddr);
- reg [1:0] state = 0; /* State within this bus cycle (see STATE_*). */
- reg [2:0] cycle = 0; /* Cycle for instructions. */
+ reg [1:0] state; /* State within this bus cycle (see STATE_*). */
+ reg [2:0] cycle; /* Cycle for instructions. */
reg [7:0] registers[11:0];
reg [7:0] opcode; /* Opcode from the current machine cycle. */
reg [7:0] rdata, wdata; /* Read data from this bus cycle, or write data for the next. */
- reg rd = 1, wr = 0, newcycle = 1;
+ reg rd, wr, newcycle;
reg [7:0] tmp, tmp2; /* Generic temporary regs. */
reg [7:0] buswdata;
assign busdata = buswr ? buswdata : 8'bzzzzzzzz;
- reg ie = 0;
+ reg ie = 0, iedelay = 0;
initial begin
registers[ 0] <= 0;
registers[ 9] <= 0;
registers[10] <= 0;
registers[11] <= 0;
- ie <= 0;
rd <= 1;
wr <= 0;
newcycle <= 1;
state <= 0;
cycle <= 0;
+ busrd <= 0;
+ buswr <= 0;
+ busaddress <= 0;
+ ie <= 0;
+ iedelay <= 0;
+ opcode <= 0;
+ state <= `STATE_WRITEBACK;
+ cycle <= 0;
end
always @(posedge clk)
end
`STATE_DECODE: begin
if (newcycle) begin
- opcode <= busdata;
+ if (ie && irq)
+ opcode <= `INSN_VOP_INTR;
+ else
+ opcode <= busdata;
rdata <= busdata;
newcycle <= 0;
cycle <= 0;
if (rd) rdata <= busdata;
cycle <= cycle + 1;
end
+ if (iedelay) begin
+ ie <= 1;
+ iedelay <= 0;
+ end
buswr <= 0;
busrd <= 0;
wr <= 0;
`define EXEC_NEWCYCLE \
newcycle <= 1; rd <= 1; wr <= 0
casex (opcode)
- `INSN_LD_reg_imm8: begin
- case (cycle)
- 0: begin
- `EXEC_INC_PC;
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
- end
- 1: begin
- `EXEC_INC_PC;
- if (opcode[5:3] == `INSN_reg_dHL) begin
- address <= {registers[`REG_H], registers[`REG_L]};
- wdata <= rdata;
- rd <= 0;
- wr <= 1;
- end else begin
- `EXEC_NEWCYCLE;
- end
- end
- 2: begin
- `EXEC_NEWCYCLE;
- end
- endcase
- end
- `INSN_HALT: begin
- `EXEC_NEWCYCLE;
- /* XXX Interrupts needed for HALT. */
- end
- `INSN_LD_HL_reg: begin
- case (cycle)
- 0: begin
- case (opcode[2:0])
- `INSN_reg_A: wdata <= registers[`REG_A];
- `INSN_reg_B: wdata <= registers[`REG_B];
- `INSN_reg_C: wdata <= registers[`REG_C];
- `INSN_reg_D: wdata <= registers[`REG_D];
- `INSN_reg_E: wdata <= registers[`REG_E];
- `INSN_reg_H: wdata <= registers[`REG_H];
- `INSN_reg_L: wdata <= registers[`REG_L];
- endcase
- address <= {registers[`REG_H], registers[`REG_L]};
- wr <= 1; rd <= 0;
- end
- 1: begin
- `EXEC_INC_PC;
- `EXEC_NEWCYCLE;
- end
- endcase
- end
- `INSN_LD_reg_HL: begin
- case(cycle)
- 0: begin
- address <= {registers[`REG_H], registers[`REG_L]};
- rd <= 1;
- end
- 1: begin
- tmp <= rdata;
- `EXEC_INC_PC;
- `EXEC_NEWCYCLE;
- end
- endcase
- end
- `INSN_LD_reg_reg: begin
- `EXEC_INC_PC;
- `EXEC_NEWCYCLE;
- case (opcode[2:0])
- `INSN_reg_A: tmp <= registers[`REG_A];
- `INSN_reg_B: tmp <= registers[`REG_B];
- `INSN_reg_C: tmp <= registers[`REG_C];
- `INSN_reg_D: tmp <= registers[`REG_D];
- `INSN_reg_E: tmp <= registers[`REG_E];
- `INSN_reg_H: tmp <= registers[`REG_H];
- `INSN_reg_L: tmp <= registers[`REG_L];
- endcase
- end
- `INSN_LD_reg_imm16: begin
- `EXEC_INC_PC;
- case (cycle)
- 0: begin
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
- end
- 1: begin
- `EXEC_NEXTADDR_PCINC;
- rd <= 1;
- end
- 2: begin `EXEC_NEWCYCLE; end
- endcase
- end
- `INSN_LD_SP_HL: begin
- case (cycle)
- 0: begin
- tmp <= registers[`REG_H];
- end
- 1: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- tmp <= registers[`REG_L];
- end
- endcase
- end
- `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
- case (cycle)
- 0: begin
- wr <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
- case (opcode[5:4])
- `INSN_stack_AF: wdata <= registers[`REG_A];
- `INSN_stack_BC: wdata <= registers[`REG_B];
- `INSN_stack_DE: wdata <= registers[`REG_D];
- `INSN_stack_HL: wdata <= registers[`REG_H];
- endcase
- end
- 1: begin
- wr <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]}-1;
- case (opcode[5:4])
- `INSN_stack_AF: wdata <= registers[`REG_F];
- `INSN_stack_BC: wdata <= registers[`REG_C];
- `INSN_stack_DE: wdata <= registers[`REG_E];
- `INSN_stack_HL: wdata <= registers[`REG_L];
- endcase
- end
- 2: begin /* Twiddle thumbs. */ end
- 3: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- endcase
- end
- `INSN_POP_reg: begin /* POP is 12 cycles! */
- case (cycle)
- 0: begin
- rd <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]};
- end
- 1: begin
- rd <= 1;
- address <= {registers[`REG_SPH],registers[`REG_SPL]};
- end
- 2: begin
- `EXEC_NEWCYCLE;
- `EXEC_INC_PC;
- end
- endcase
- end
+ `define EXECUTE
+ `include "allinsns.v"
+ `undef EXECUTE
`INSN_LDH_AC: begin
case (cycle)
0: begin
end
endcase
end
- default:
- $stop;
- endcase
- state <= `STATE_WRITEBACK;
- end
- `STATE_WRITEBACK: begin
- casex (opcode)
- `INSN_LD_reg_imm8:
+ `INSN_VOP_INTR: begin
case (cycle)
- 0: begin end
- 1: case (opcode[5:3])
- `INSN_reg_A: begin registers[`REG_A] <= rdata; end
- `INSN_reg_B: begin registers[`REG_B] <= rdata; end
- `INSN_reg_C: begin registers[`REG_C] <= rdata; end
- `INSN_reg_D: begin registers[`REG_D] <= rdata; end
- `INSN_reg_E: begin registers[`REG_E] <= rdata; end
- `INSN_reg_H: begin registers[`REG_H] <= rdata; end
- `INSN_reg_L: begin registers[`REG_L] <= rdata; end
- `INSN_reg_dHL: begin /* Go off to cycle 2 */ end
- endcase
- 2: begin end
- endcase
- `INSN_HALT: begin
- /* Nothing needs happen here. */
- /* XXX Interrupts needed for HALT. */
- end
- `INSN_LD_HL_reg: begin
- /* Nothing of interest here */
- end
- `INSN_LD_reg_HL: begin
- case (cycle)
- 0: begin end
- 1: begin
- case (opcode[5:3])
- `INSN_reg_A: registers[`REG_A] <= tmp;
- `INSN_reg_B: registers[`REG_B] <= tmp;
- `INSN_reg_C: registers[`REG_C] <= tmp;
- `INSN_reg_D: registers[`REG_D] <= tmp;
- `INSN_reg_E: registers[`REG_E] <= tmp;
- `INSN_reg_H: registers[`REG_H] <= tmp;
- `INSN_reg_L: registers[`REG_L] <= tmp;
- endcase
+ 0: begin
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} - 1;
+ wdata <= registers[`REG_PCH];
+ wr <= 1;
end
- endcase
- end
- `INSN_LD_reg_reg: begin
- case (opcode[5:3])
- `INSN_reg_A: registers[`REG_A] <= tmp;
- `INSN_reg_B: registers[`REG_B] <= tmp;
- `INSN_reg_C: registers[`REG_C] <= tmp;
- `INSN_reg_D: registers[`REG_D] <= tmp;
- `INSN_reg_E: registers[`REG_E] <= tmp;
- `INSN_reg_H: registers[`REG_H] <= tmp;
- `INSN_reg_L: registers[`REG_L] <= tmp;
- endcase
- end
- `INSN_LD_reg_imm16: begin
- case (cycle)
- 0: begin /* */ end
1: begin
- case (opcode[5:4])
- `INSN_reg16_BC: registers[`REG_C] <= rdata;
- `INSN_reg16_DE: registers[`REG_E] <= rdata;
- `INSN_reg16_HL: registers[`REG_L] <= rdata;
- `INSN_reg16_SP: registers[`REG_SPL] <= rdata;
- endcase
+ address <= {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ wdata <= registers[`REG_PCL];
+ wr <= 1;
end
- 2: begin
- case (opcode[5:4])
- `INSN_reg16_BC: registers[`REG_B] <= rdata;
- `INSN_reg16_DE: registers[`REG_D] <= rdata;
- `INSN_reg16_HL: registers[`REG_H] <= rdata;
- `INSN_reg16_SP: registers[`REG_SPH] <= rdata;
- endcase
+ 2: begin
+ `EXEC_NEWCYCLE;
end
endcase
end
- `INSN_LD_SP_HL: begin
- case (cycle)
- 0: registers[`REG_SPH] <= tmp;
- 1: registers[`REG_SPL] <= tmp;
- endcase
- end
- `INSN_PUSH_reg: begin /* PUSH is 16 cycles! */
- case (cycle)
- 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- 1: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} - 1;
- 2: begin /* type F */ end
- 3: begin /* type F */ end
- endcase
+ `INSN_DI: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
end
- `INSN_POP_reg: begin /* POP is 12 cycles! */
- case (cycle)
- 0: {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
- 1: begin
- case (opcode[5:4])
- `INSN_stack_AF: registers[`REG_F] <= rdata;
- `INSN_stack_BC: registers[`REG_C] <= rdata;
- `INSN_stack_DE: registers[`REG_E] <= rdata;
- `INSN_stack_HL: registers[`REG_L] <= rdata;
- endcase
- {registers[`REG_SPH],registers[`REG_SPL]} <=
- {registers[`REG_SPH],registers[`REG_SPL]} + 1;
- end
- 2: begin
- case (opcode[5:4])
- `INSN_stack_AF: registers[`REG_A] <= rdata;
- `INSN_stack_BC: registers[`REG_B] <= rdata;
- `INSN_stack_DE: registers[`REG_D] <= rdata;
- `INSN_stack_HL: registers[`REG_H] <= rdata;
- endcase
- end
- endcase
+ `INSN_EI: begin
+ `EXEC_NEWCYCLE;
+ `EXEC_INC_PC;
end
+ default:
+ $stop;
+ endcase
+ state <= `STATE_WRITEBACK;
+ end
+ `STATE_WRITEBACK: begin
+ casex (opcode)
+ `define WRITEBACK
+ `include "allinsns.v"
+ `undef WRITEBACK
`INSN_LDH_AC: begin
case (cycle)
0: begin /* Type F */ end
registers[`REG_F] <= {registers[`REG_F][7],1'b1,1'b1,registers[`REG_F][4:0]};
end
`INSN_alu_SCF: begin
- registers[`REG_F] <= {registers[`REG_F][7:5],1,registers[`REG_F][3:0]};
+ registers[`REG_F] <= {registers[`REG_F][7:5],1'b1,registers[`REG_F][3:0]};
end
`INSN_alu_CCF: begin
registers[`REG_F] <= {registers[`REG_F][7:5],~registers[`REG_F][4],registers[`REG_F][3:0]};
end
endcase
end
+ `INSN_VOP_INTR: begin
+ case (cycle)
+ 0: begin end
+ 1: begin end
+ 2: begin
+ ie <= 0;
+ {registers[`REG_PCH],registers[`REG_PCL]} <=
+ {8'b0,jaddr};
+ {registers[`REG_SPH],registers[`REG_SPL]} <=
+ {registers[`REG_SPH],registers[`REG_SPL]} - 2;
+ end
+ endcase
+ end
+ `INSN_DI: ie <= 0;
+ `INSN_EI: iedelay <= 1;
default:
$stop;
endcase
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